FIR II IP Intel® FPGA IP: User Guide

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ID 683208
Date 5/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Intel® FPGA IP 2. FIR II IP Getting Started 3. FIR II IP Parameters 4. FIR II IP Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Testbench in MATLAB 2.6. DSP Builder Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
3. FIR II IP Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Multiple Coefficient Banks 4.6. FIR II IP Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Signals 4.8.4. FIR Filter Reset
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Intel® FPGA IP
2. FIR II IP Getting Started
3. FIR II IP Parameters
4. FIR II IP Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

3.5. FIR II IP Core Implementation Options

Table 13.  Implementation Options Parameters
Parameter Value Description
Resource Optimization Settings
Device Family Menu of supported devices The target device family.
Speed grade Fast, medium, slow The speed grade of the target device.
Memory Block Threshold Integer The balance of resources between LEs and small RAM block threshold in bits.
Dual Port RAM Threshold Integer The balance of resources between small and medium RAM block threshold in bits.
Large RAM Threshold Integer The balance of resources between medium and large RAM block threshold in bits.
Hard Multiplier Threshold Integer The balance of resources between LEs and DSP block multiplier threshold in bits. The default value is -1.
Internal Delay-Lines Rezeroed on Warm-Reset Off or on Turn on to make the IP effectively rezero internal delay-line memories on a warm reset. When off, internal delay lines may contain residual data after a warm reset that may then affect the subsequent initial filter response. When on, the initial filter response after a warm reset is identical to its response after a power-on reset (as if all internal delay lines are zero). When on, you may see a resource increase.The MATLAB model offers no means of reset.
Simulation Tests Warm-Reset Off or on Turn on to make the HDL simulation testbench test the rezeroing of delay lines on a warm reset. The testbench injects a reset after the final nonzero input. After this reset, the testbench checks that the IP zeros all valid output. The input before the warm reset leaves no residual effect on the output after warm reset. Injecting the warm reset is a convenience that simplifies the expected result checking.The MATLAB model has no reset test capability, only the HDL testbench.
Coefficent Sharing off, auto

Coefficient sharing means the FIR IP uses a single copy of coefficients when your FIR configuration requires the same coefficient values in multiple parallel calculations.

Coefficient sharing can give a significant resource reduction. Look at the Resource Estimation to see the effect this parameter has on resource usage.

When you select off, the IP never applies coefficient sharing, which is legacy (unoptimized) FIR behavior.

When you select auto, Quartus Prime applies coefficient sharing if possible. If your FIR filter has multiple banks, Quartus Primes does not apply it, as it affects the FIR interface. The Quartus Prime report indicates when coefficient sharing is applied. Coefficient sharing may have no effect on Resource Estimation even if Quartus Prime applies it (for example, if the DSPs of your target device absorb the coefficients).

The default value is off.

Reset Minimization off, on, auto

Reset minimization reduces the amount of reset logic in your design

When you select auto or on, the FIR IP resets only essential logic.

A reduction in reset logic can give an area decrease and potential fMAX increase. Look at the Resource Estimation to see the effect this parameter has on resource usage.

When you select off, the IP applies no reset minimization, which is legacy (unoptimized) FIR behavior.

When you select auto, reset minimization is applied only if targeting a Hyperflex device family.

When you select on, the IP applies reset minimization.

The default value is off.

Resource Estimation
Number of LUTs - Shows the number of LUTs.
Number of DSPs - Shows the number of DSPs.
Number of memory bits - Shows the number of memory bits.

Section Content
Memory and Multiplier Trade-Offs

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