Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 4/01/2024
Public
Document Table of Contents

2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency

In this example, the source clock frequency value of 5 ns is an integer multiple of the destination clock frequency of 10 ns. The source clock frequency can be an integer multiple of the destination clock frequency when a PLL generates both clocks and use different multiplication and division factors.

In the following example the source clock frequency is a multiple of the destination clock frequency:

Figure 138. Source Clock Frequency is Multiple of Destination Clock Frequency:

The following timing diagram shows the default setup check analysis the Timing Analyzer performs:

Figure 139. Default Setup Check Analysis
Figure 140. Setup Check Calculation

The setup relationship demonstrates that the data launched at edge one does not require capture, and the data launched at edge two requires capture; therefore, you can relax the setup requirement. To correct the default analysis, you shift the launch edge by one clock period with a start multicycle setup exception of two. The following multicycle exception adjusts the default analysis in this example:

Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
     -setup -start 2

The following timing diagram shows the preferred setup relationship for this example:

Figure 141. Preferred Setup Check Analysis

The following timing diagram shows the default hold check analysis the Timing Analyzer performs for a start multicycle setup value of two:

Figure 142. Default Hold Check
Figure 143. Hold Check Calculation

In this example, the hold check two is too restrictive. The data is launched next by the edge at 10 ns and must check against the data captured by the current latch edge at 10 ns, which does not occur in hold check two. To correct the default analysis, you use a start multicycle hold exception of one.