AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.4.2. Plan the PCIe* Interface

The Interface Planner helps you to locate available locations and pin placement for the Intel® FPGA IP for PCIe* and the SerialLite III Intel® FPGA IP interfaces. The following sections describe planning for these IP.

Follow these steps to plan the PCIe* interface:

  1. In Interface Planner, click the IP filter button.
  2. In the Design Elements list, expand the IP_TOP_I0 block to select the PCIe* dut design element. The design example FPGA_TOP.vhd file specifies to only use the left side of the device.
  3. Click the >> button next to dut to display Legal Locations for placement. Interface Planner shows one legal location for the left side of the device.
    Figure 12. Legal Locations Button
  4. Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_24 to place the elements in the floorplan. This placement then assigns this PCIe* IP to this fixed location.
    Figure 13. PCIe Fixed Placement
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