Qsys System Design Tutorial

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ID 683378
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Qsys System Design Tutorial
1. Qsys System Design Tutorial x
1.1. Software and Hardware Requirements 1.2. Download and Install the Tutorial Design Files 1.3. Open the Tutorial Project 1.4. Creating Qsys Systems 1.5. Assemble a Hierarchical System 1.6. Viewing the Memory Tester System in Qsys 1.7. Compiling and Downloading Software to a Development Board 1.8. Debugging Your Design 1.9. Verifying Hardware in System Console 1.10. Simulating Custom Components 1.11. View a Diagram of the Completed System
1.4. Creating Qsys Systems x
1.4.1. Create a Data Pattern Generator Qsys System 1.4.2. Create a Data Pattern Checker Qsys System
1.4.1. Create a Data Pattern Generator Qsys System x
1.4.1.1. Create a New Qsys System and Set up the Clock Source 1.4.1.2. Add a Pipeline Bridge 1.4.1.3. Add a Custom Pattern Generator 1.4.1.4. Add a PRBS Pattern Generator 1.4.1.5. Add a Two-to-One Streaming Multiplexer 1.4.1.6. Verify the Memory Address Map 1.4.1.7. Connect the Reset Signals 1.4.1.8. Save the System
1.4.2. Create a Data Pattern Checker Qsys System x
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource 1.4.2.2. Add a Pipeline Bridge 1.4.2.3. Add a Custom Pattern Checker 1.4.2.4. Add the PRBS Pattern Checker 1.4.2.5. Add a One-to-Two Streaming Demultiplexer 1.4.2.6. Verify the Memory Address Map 1.4.2.7. Connect the Reset Signals 1.4.2.8. Save the System
1.5. Assemble a Hierarchical System x
1.5.1. Create the Hierarchical Memory Tester System 1.5.2. Complete the Top-Level System
1.5.1. Create the Hierarchical Memory Tester System x
1.5.1.1. Add the Pattern Generator 1.5.1.2. Add the Pattern Checker 1.5.1.3. Add Memory Master Components 1.5.1.4. Connect the Reset Signals 1.5.1.5. Verify the Memory Address Map 1.5.1.6. Save the System
1.5.1.3. Add Memory Master Components x
1.5.1.3.1. Add a Pattern Writer Component 1.5.1.3.2. Add a Pattern Reader Component 1.5.1.3.3. Add a RAM Test Controller
1.9. Verifying Hardware in System Console x
1.9.1. Open the Tutorial Project 1.9.2. Add the JTAG-to-Avalon Master Bridge 1.9.3. Debug with System Console
1.10. Simulating Custom Components x
1.10.1. Generate a Testbench System in Qsys 1.10.2. Run Simulation In the ModelSim-Altera Software
1.10.1. Generate a Testbench System in Qsys x
1.10.1.1. Create a New Qsys System for the Design Under Test 1.10.1.2. Export Design Under Test 1.10.1.3. Generate a Testbench System 1.10.1.4. Generate Testbench System's Simulation Models
1.10.2. Run Simulation In the ModelSim-Altera Software x
1.10.2.1. Set Up the Simulation Environment 1.10.2.2. Run the Simulation
1. Qsys System Design Tutorial

1.10.1.4. Generate Testbench System's Simulation Models

In this section, you open the generated Qsys testbench system and rename the BFM component instance names to ensure the testbench names match the test program provided with the tutorial design files. Additionally, you generate the testbench's simulation model.
  1. In Qsys, open the testbench system, pattern_generator_tb.qsys, from the simulation_tutorial\pattern_generator\testbench directory.
  2. On the System Contents tab, rename the instance as they appear in Table 5–1.
    Qsys-Generated Components' Names New Instance Name
    pattern_generator_inst DUT
    pattern_generator_inst_pg_clock_bfm clock_source
    pattern_generator_inst_pg_reset_bfm reset_source
    pattern_generator_inst_pg_csr_bfm csr_master
    pattern_generator_inst_pg_pattern_access_bfm pattern_master
    pattern_generator_inst_pg_pattern_output_bfm pattern_sink
  3. Double-click a BFM component to open the parameter editor and view its settings. These BFM components are available in the Avalon Verification Suite group in the library. If necessary, you can change the parameters for the BFMs to ensure adequate test coverage for your design.
    The Qsys-generated testbench matches inserted BFMs with the exported interfaces from the design that they drive. The test program that provides stimulus to the BFMs must account for the matching interface. For example, an exported Avalon-MM slave interface (which expects word-aligned addresses) is connected to an Avalon master BFM, which expects and transacts word-aligned addresses instead of the byte or symbol addresses that are default for Avalon masters.
  4. Click Cancel to close the parameter editor without making changes.
  5. In the Generation dialog box, under Simulation, for Create simulation model, select Verilog.
  6. Under Testbench System, select None for Create testbench Qsys system and Create testbench simulation model.
  7. Under Synthesis, select None for Create HDL design files for synthesis, and turn off Create Block design files (.bsf).
  8. Save the system.
  9. Click Generate.
  10. After Qsys generates the testbench, click Close.

Qsys generates the testbench system’s simulation models in the \simulation_tutorial\pattern_generator\testbench\pattern_generator_tb\simulation directory.

Qsys generates the simulation models and a ModelSim simulation script (msim_setup.tcl), which compiles the required files for simulation and sets up commands to load the simulation in the ModelSim simulator. You can run this ModelSim script in ModelSim-Altera to compile, elaborate, or load for simulation.

In this tutorial, there is an external test program to provide simulation stimulus. The tutorial design files include a simulation script, load_sim.tcl that compiles the top-level simulation file and test program, and calls the Qsys-generated script to compile the required files.

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