AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone® 10 GX FPGA Development Board

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ID 683548
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board

Reference Design Requirements

This reference design requires the following:

  • Intel® Quartus® Prime Pro Edition software version 19.1 for the design implementation.
  • Intel Cyclone® 10 GX FPGA development kit for the FPGA implementation.
Level Two Title