AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone® 10 GX FPGA Development Board

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ID 683548
Date 7/15/2019
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board

Step 11: Programming the Board

Before you begin:
  1. Connect the power supply to the Intel Cyclone® 10 GX FPGA development board.
  2. Connect the Intel® FPGA Download Cable between your PC USB port and the Intel® FPGA Download Cable port on the development board.

To run the design on the Intel Cyclone® 10 GX FPGA development board:

  1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select USB-Blaster.
  3. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
  4. Enable Program/Configure for blinking_led.sof file.
  5. Click Start and wait for the progress bar to reach 100%.
  6. Observe the LEDs on the board blinking at the same frequency as the original flat design.
  7. To program only the child PR region, right-click the blinking_led.sof file in the Programmer and click Add PR Programming File.
  8. Select the hpr_child_slow.pr_parent_partition.pr_partition.rbf file.
  9. Disable Program/Configure for the blinking_led.sof file.
  10. Enable Program/Configure for the hpr_child_slow.pr_parent_partition.pr_partition.rbf file and click Start. On the board, observe LED[0], LED[1], and LED[2] continuing to blink. When the progress bar reaches 100%, LED[3] blinks slower
  11. To program both the parent and child PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
  12. Select the hpr_child_empty.pr_parent_partition.rbf file.
  13. Click Start. On the board, observe that LED[0], LED[1] and LED[2] continue to blink. When the progress bar reaches 100%, LED[3] turns off.
  14. Repeat the above steps to dynamically re-program just the child PR region, or both the parent and child PR regions simultaneously.
Figure 20. Programming the Intel Cyclone® 10 GX FPGA Development Board
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