Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Public
Document Table of Contents

10.6.1. Boundary-Scan Cells of a Stratix V Device I/O Pin

The Stratix® V device 3-bit BSC consists of the following registers:

  • Capture registers—Connect to internal device data through the OUTJ, OEJ, and PIN_IN signals.
  • Update registers—Connect to external data through the PIN_OUT and PIN_OE signals.

The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (shift, clock, and update) internally. A decode of the instruction register generates the MODE signal.

The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.

Figure 197. User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Stratix V Devices


Note: TDI, TDO, TMS, and TCK pins, all VCC and GND pin types, and VREF pins do not have BSCs.
Table 101.   Boundary-Scan Cell Descriptions for Stratix V DevicesThis table lists the capture and update register capabilities of all BSCs within Stratix® V devices.
Pin Type Captures Drives Comments
Output Capture Register OE Capture Register Input Capture Register Output Update Register OE Update Register Input Update Register
User I/O pins OUTJ OEJ PIN_IN PIN_OUT PIN_OE INJ
Dedicated clock input 0 1 PIN_IN No Connect (N.C.) N.C. N.C. PIN_IN drives to the clock network or logic array
Dedicated input 0 1 PIN_IN N.C. N.C. N.C. PIN_IN drives to the control logic
Dedicated bidirectional (open drain)27 0 OEJ PIN_IN N.C. N.C. N.C. PIN_IN drives to the configuration control
Dedicated bidirectional28 OUTJ OEJ PIN_IN N.C. N.C. N.C. PIN_IN drives to the configuration control and OUTJ drives to the output buffer
Dedicated output29 OUTJ 0 0 N.C. N.C. N.C. OUTJ drives to the output buffer
27 This includes the CONF_DONE and nSTATUS pins.
28 This includes the DCLK pin.
29 This includes the nCEO pin.