AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

Download PDF
ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.3. FPGA Pin Assignments

The top-level signals with its corresponding FPGA pin assignments on the Intel® Arria® 10 GX FPGA development board are listed in the table below.

Table 14.  Top Level Signals with Corresponding FPGA Pin, IO Standard and DirectionIn this design, the PIO internally generates the SYSREF signal in the Nios II Subsystem.
Top Level Signal Name FPGA Pin Number I/O Standard Direction
global_rst_n T12 1.8V Input
device_clk AC8 LVDS Input
device_clk (n) AC7 LVDS Input
mgmt_clk AR36 LVDS Input
mgmt_clk (n) AR37 LVDS Input
tx_serial_data[0] BC7 High Speed Differential I/O Output
tx_serial_data[0] (n) BC8 High Speed Differential I/O Output
tx_serial_data[1] BD5 High Speed Differential I/O Output
tx_serial_data[1] (n) BD6 High Speed Differential I/O Output
tx_serial_data[2] BB5 High Speed Differential I/O Output
tx_serial_data[2] (n) BB6 High Speed Differential I/O Output
tx_serial_data[3] BC3 High Speed Differential I/O Output
tx_serial_data[3] (n) BC4 High Speed Differential I/O Output
tx_serial_data[4] BB1 High Speed Differential I/O Output
tx_serial_data[4] (n) BB2 High Speed Differential I/O Output
tx_serial_data[5] BA3 High Speed Differential I/O Output
tx_serial_data[5] (n) BA4 High Speed Differential I/O Output
tx_serial_data[6] AY1 High Speed Differential I/O Output
tx_serial_data[6] (n) AY2 High Speed Differential I/O Output
tx_serial_data[7] AW3 High Speed Differential I/O Output
tx_serial_data[7] (n) AW4 High Speed Differential I/O Output
tx_serial_data[8] AV1 High Speed Differential I/O Output
tx_serial_data[8] (n) AV2 High Speed Differential I/O Output
tx_serial_data[9] AU3 High Speed Differential I/O Output
tx_serial_data[9] (n) AU4 High Speed Differential I/O Output
tx_serial_data[10] AT1 High Speed Differential I/O Output
tx_serial_data[10] (n) AT2 High Speed Differential I/O Output
tx_serial_data[11] AR3 High Speed Differential I/O Output
tx_serial_data[11] (n) AR4 High Speed Differential I/O Output
tx_serial_data[12] AP1 High Speed Differential I/O Output
tx_serial_data[12] (n) AP2 High Speed Differential I/O Output
tx_serial_data[13] AM1 High Speed Differential I/O Output
tx_serial_data[13] (n) AM2 High Speed Differential I/O Output
tx_serial_data[14] AK1 High Speed Differential I/O Output
tx_serial_data[14] (n) AK2 High Speed Differential I/O Output
tx_serial_data[15] AH1 High Speed Differential I/O Output
tx_serial_data[15] (n) AH2 High Speed Differential I/O Output
rx_serial_data[0] AW7 High Speed Differential I/O Input
rx_serial_data[0] (n) AW8 High Speed Differential I/O Input
rx_serial_data[1] BA7 High Speed Differential I/O Input
rx_serial_data[1] (n) BA8 High Speed Differential I/O Input
rx_serial_data[2] AY5 High Speed Differential I/O Input
rx_serial_data[2] (n) AY6 High Speed Differential I/O Input
rx_serial_data[3] AV5 High Speed Differential I/O Input
rx_serial_data[3] (n) AV6 High Speed Differential I/O Input
rx_serial_data[4] AT5 High Speed Differential I/O Input
rx_serial_data[4] (n) AT6 High Speed Differential I/O Input
rx_serial_data[5] AP5 High Speed Differential I/O Input
rx_serial_data[5] (n) AP6 High Speed Differential I/O Input
rx_serial_data[6] AN3 High Speed Differential I/O Input
rx_serial_data[6] (n) AN4 High Speed Differential I/O Input
rx_serial_data[7] AM5 High Speed Differential I/O Input
rx_serial_data[7] (n) AM6 High Speed Differential I/O Input
rx_serial_data[8] AL3 High Speed Differential I/O Input
rx_serial_data[8] (n) AL4 High Speed Differential I/O Input
rx_serial_data[9] AK5 High Speed Differential I/O Input
rx_serial_data[9] (n) AK6 High Speed Differential I/O Input
rx_serial_data[10] AJ3 High Speed Differential I/O Input
rx_serial_data[10] (n) AJ4 High Speed Differential I/O Input
rx_serial_data[11] AH5 High Speed Differential I/O Input
rx_serial_data[11] (n) AH6 High Speed Differential I/O Input
rx_serial_data[12] AG3 High Speed Differential I/O Input
rx_serial_data[12] (n) AG4 High Speed Differential I/O Input
rx_serial_data[13] AF5 High Speed Differential I/O Input
rx_serial_data[13] (n) AF6 High Speed Differential I/O Input
rx_serial_data[14] AE3 High Speed Differential I/O Input
rx_serial_data[14] (n) AE4 High Speed Differential I/O Input
rx_serial_data[15] AD5 High Speed Differential I/O Input
rx_serial_data[15] (n) AD6 High Speed Differential I/O Input
sync_n_in AR15 LVDS Input
sync_n_in (n) AT15 LVDS Input
sync_n_out AT17 LVDS Output
sync_n_out (n) AU17 LVDS Output
user_led_g[0] D18 1.8V Output
user_led_g[1] C18 1.8V Output
user_led_g[2] A19 1.8V Output
user_led_g[3] J24 1.8V Output
user_led_g[4] L25 1.8V Output
user_led_g[5] K25 1.8V Output
user_led_g[6] K26 1.8V Output
user_led_g[7] L28 1.8V Output
Level Two Title