Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector

Intel recommends staggered placement for AC coupling capacitors for ease of routing and crosstalk control. Ensure the top layer microstrip trace length from AC coupling capacitor to MCIO connector pin is as short as practical per DFM requirements. Optimize the open field PCB layout to improve the NEXT and FEXT.
Figure 36. AC Coupling Capacitor Staggered Placement Around the MCIO ConnectorThis example shows the crosstalk simulation results based on the Intel Agilex® 7 F-Series FPGA Development Board. Red represents TX on layer7, yellow represents RX on layer5, blue represents GND.

Figure 37. Simulation ResultsThe figures show two TX pairs and one RX pair. The simulation includes an AC coupling capacitor, via, part of the microstrip trace and part of the strip-line trace. The simulation results show the NEXT is less than -60.0dB up to 16.0 GHz; the FEXT is less than -50.0dB up to 16.0 GHz.
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