Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area

This design example on the PCIe development board uses the breakout trace width and space of 3.35mil and 4.65mil. The TX routes on layer3 and RX routes on layer16 because of the pin definition of the Mini Cool Edge IO (MCIO) connector (the PCIe channels connect FPGA and MCIO connector). The connector TX pins are located at the side near FPGA. The RX pins are located at the opposite side to the FPGA. The RX traces route underneath the MCIO connector pin cut-out if RX traces route on layer3.
Figure 33. MCIO Connector Fan-out Design Example

Red represents TX on layer3, yellow represents RX on layer16, blue represents GND. Includes two vias per ground pin to reduce the ground parasitic effect. Route the micro-strip trace length on the top and bottom as short as possible.

Figure 34. R-tile Breakout Routing Example in BGA Pin Field AreaDark blue represents TX on layer3 (by micro via, top to layer3), red represents RX on layer16 (by through hole via, top to layer16), blue represents GND.
Figure 35. R-tile Breakout Routing Crosstalk Simulation ResultsThe figures show four TX pairs and four RX pairs. The simulation includes FPGA BGA ball, BGA via, breakout trace, and part of main routing. The simulation results show the near end crosstalk (NEXT) is less than -60.0dB up to 16.0 GHz, the far end crosstalk (FEXT) is less than -50.0dB up to 16.0 GHz.
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