Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.5. R-Tile PCB Guidelines

R-Tile is PCIe Gen5 transceiver tile.

All the P-tile guidelines apply to R-tile devices. Additionally, the following guidelines are for R-tile devices running at 32 Gbps data rate:

  • Intel guarantees the insertion loss of the FPGA package plus the silicon does not exceed 4.0dB at 16 GHz.
  • Ensure the R-tile high speed signal (HSSI) via stub is as short as possible through back-drill or micro via techniques. Intel recommends a stub length smaller than 10 mils. Long via stubs reduce the via impedance and produce resonances at low frequencies that worsen the channel insertion loss and return loss.
    Figure 28. Insertion loss curve of a differential via pair with different via stub length
  • Use a short coupling length between HSSI vias, where the via stub is part of via length.
  • Assigning suitable routing layers to high speed Tx and Rx signals obtain better Rx performance and less crosstalk between Tx breakout traces and Rx vias after implementing back-drilling or micro via techniques.
    Figure 29. R-tile Hex Pin Pattern Blue represents the GND, green represents R-tile HSSI Differential Pairs
  • Improve the HSSI TX and RX breakout routing in the pin field area. This routing strategy reduces breakout area signal trace to via coupling. The larger distance between breakout trace and adjacent signal vias, the smaller crosstalk; the smaller the coupling area between breakout trace and adjacent signal vias, the smaller the crosstalk.
    Figure 30. Recommended Patterns The figure shows the examples of recommended breakout pattern to minimize the trace to via coupling. Each differential via pair has a short bar connecting the P and N together just for indicating the differential via.
  • Optimize the breakout trace width and space based on the PCB manufacturing capabilities in BGA via field to keep the impedance matching with the main routing is recommended.
  • Use small package AC coupling capacitors to minimize the impedance discontinuity, e.g. 0201(inch). Ensure the capacitor landing pad is as small as possible as per the DFM requirements. Optimize the cut-out underneath the capacitor pads to improve the channel impedance continuity.
  • Ensure a tight trace impedance control, e,g, 5% or 7% depending on the specific PCB.
  • Keep the number of transition vias in the HSSI channel as few as possible. Layer transition vias in the HSSI channel typically reduce electrical performance. For example, only add vias at BGA pin, AC cap (only exist on the FPGA transmit channels), and connector pins.

Section Content
R-Tiles Features and Capabilities
R-Tile Design Layout Examples
Landing Pad Cut-out Optimization of AC Coupling Capacitor
R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area
AC Coupling Capacitor Placement Around MCIO Connector
PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines

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