4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. 4G Turbo-V Intel FPGA IP User Guide Document Archive 6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. 4G Turbo-V Intel FPGA IP User Guide Document Archive
6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

1.4. 4G Turbo-V Performance and Resource Utilization

Intel generated the resource utilization and performance by compiling the designs with Intel Quartus Prime software v23.2. Only use these approximate results for early estimation of FPGA resources (e.g. adaptive logic modules (ALMs)) that a project requires.
Table 2.  Downlink Accelerator Performance and Resources
Family Device Average fMAX (MHz) 1 ALM M20K DSP
Agilex™ 5 SM7_PART_4S 248 8.1k 51 6
A5EC065BB32AE5SR0 204 8.2k 51 6
A5EC065BB32AE6SR0 189 8.2k 51 6
Agilex™ 7 AGFB014R24B1E1V 430 8.7k 51 6
AGFB014R24B2E2V 382 8.7k 51 6
AGFB014R24B2E3V 328 8.7k 51 6

AGFB014R24B2E3E

 328 8.7k 51 6
AGFB014R24B2E4X 243 8.7k 51 6
AGFB014R24B2E4F 243 8.7k 51 6
AGFB014R24B1I1V 430 8.7k 51 6
AGFB014R24B2I2V 382 8.7k 51 6
AGFB014R24B2I3V 328 8.7k 51 6
AGFB014R24B2I3E 328 8.7k 51 6
Intel Arria 10 10AT115S1F45E1SG 288 7.7k 51 6
Intel Stratix 10 1SG280HU2F50E2VG 275 8.4k 51 6
1SG280HU2F50E2LG 263 8.4k 51 6
Table 3.  Uplink Accelerator Performance and Resource Utilization
Family Device Average fMAX (MHz) 2 ALM M20K DSP
Agilex™ 5 SM7_PART_4S 302 26.6k 45 0
A5EC065BB32AE5SR0 252 26.3k 45 0
A5EC065BB32AE6SR0 231 26.3k 45 0
Agilex™ 7 AGFB014R24B1E1V 519 28.8k 45 0
AGFB014R24B2E2V 460 28.8k 45 0
AGFB014R24B2E3V 414 28.8k 45 0

AGFB014R24B2E3E

 414 28.8k 45 0
AGFB014R24B2E4X 362 28.8k 45 0
AGFB014R24B2E4F 324 28.8k 45 0
AGFB014R24B1I1V 515 28.8k 45 0
AGFB014R24B2I2V 461 28.8k 45 0
AGFB014R24B2I3V 417 28.8k 45 0
AGFB014R24B2I3E 417 28.8k 45 0
Intel Arria 10 10AT115S1F45E1SG 304 23.8k 45 0
           
Intel Stratix 10 1SG280HU2F50E2VG 304 28.1k 45 0
1SG280HU2F50E2LG 283 28.0k 45 0
1 Reduced 15% for margin
2 Reduced 15% for margin
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