4G Turbo-V Intel® FPGA IP User Guide

ID 683882
Date 4/01/2024
Public
Document Table of Contents

3.2. Simulating the IP with the RTL Simulator

Before simulating, generate a design example from the IP parameter editor. No hardware example gets generated when you click Generate Example Design. If you upgrade the IP to a newer version, regenerate the example design.
  1. To run the simulation with Synopsys VCS® simulator, run vcsmx_setup.sh from <example_design_directory>\simulation_scripts\synopsys\vcsmx\ directory by typing the following commands:
    >> source vcsmx_setup.sh
    >> simv
  2. To run the simulation with Cadence NCSim® simulator, run ncsim_setup.sh from <example_design_directory>\simulation_scripts\cadence\ directory by typing the following command:
    sh ./ncsim_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  3. To run the simulation with Xcelium® simulator, run xcelium_setup.sh from <example_design_directory>\simulation_scripts\xcelium\ directory by typing the following command:
    sh ./xcelium_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  4. To run the simulation with the ModelSim or Questa® simulator, run msim_setup.tcl from <example_design_directory>\simulation_scripts\mentor\ directory by typing the following commands:
    vsim -c do msim_setup.tcl
    ld
    run -all
    
  5. To run the simulation with Aldec® simulator. run rivierapro_setup.tcl from <example_design_directory>\simulation_scripts\aldec\ directory by typing the following commands:
    vsim -c do rivierapro_setup.tcl
    ld
    run -all