DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683603
Date 9/02/2022
Public

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2.3.1. Intel® Cyclone® 10 GX DisplayPort SST TX-only Design Features

The TX-only design example demonstrates the transmission of a single video stream from DisplayPort Sink to DisplayPort Source.
Figure 10.  Intel® Cyclone® 10 GX DisplayPort SST TX-only
  • To generate this TX-only variant, turn on the DisplayPort source TX SUPPORT DP parameter and turn off the DisplayPort sink RX SUPPORT DP parameter.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source’s TX SUPPORT IM ENABLE parameter is turned off.
  • For video source, this variant integrates Test Pattern Generator II and Clocked Video Output II to display 1080p60 color bar image.
  • The IOPLL drives the video clock at a 300 MHz to CVO II and 37.125 Mhz (4 pixel per clock) to TPG II.
  • Before programming SOF file to the development kit, set OUT6 frequency of Si5332 (U64) to 100 MHz in the Clock Control GUI for the tx_vid_pll reference clock. If you already have a clock pin with a 100 MHz frequency, you do not need to configure the clock. Just feed in 100 MHz clock to tx_vid_pll reference clock.