DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683603
Date 9/02/2022
Public

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2. Parallel Loopback Design Examples

The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Table 7.   DisplayPort Intel® FPGA IP Design Example for Intel® Cyclone® 10 GX Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST TX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex -
DisplayPort SST RX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex -
DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR
DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR
DisplayPort MST parallel loopback with PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR
DisplayPort MST parallel loopback without PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR