AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

Hyper-Retimer Restrictions

The Hyper-Retimer balances register chains by retiming ALM registers into Hyper-Registers in the routing fabric.

The Design Assistant rules that identify retiming restrictions prevent the Hyper-Retimer from making optimizations in Agilex™ 7 and Intel Stratix 10 devices, thus limiting performance. Such restrictions include asynchronous resets, high fan-out nets, timing exceptions, the preserve register attributes, and initial conditions. The Design Assistant rules are:

  • TMC-20204 – nodes with retiming restrictions that may restrict retiming
  • TMC-20205 – nodes with initial conditions that may restrict retiming
  • HRR-10003 – registers with high fan-out non-globals
Note: TMC-20204 and TMC-20205 only look at the worst setup-failing paths in the design. They do not report on retiming restrictions or initial conditions in off-critical logic.

Fast forward compile identifies the critical chain and points out the next steps to take to remove the retiming restrictions, if possible. For more information about hyper-retiming restrictions, refer to the Intel Hyperflex Architecture High-Performance Design Handbook.

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