Initial Power-Up Conditions Rules
The initial condition of the design at power-up represents the state of the design at clock cycle 0. This state is transitional rather than functional because the design cannot return to this condition.
| Rule | Description | Possible course of action |
| HRR-10203 | Catches registers whose initial conditions drop because of IGNORE_REGISTER_POWER_UP_INITIALIZATION ON | Verify that the design is still functionally correct without these initial conditions. |
| RES-30132 | Registers might not be properly reset | Check to see if you need these registers. |
| RES-30133 | Catches memories that may have spurious writes because of initial conditions | Check to see that these registers are reset. |
| HRR-10201 | Power-up don’t care synthesis setting might prevent retiming | Remove power-up don’t care setting |
| TMC-20205 | Setup-failing path endpoints with explicit power-up states that might restrict retiming | Use QSFs to ignore initial conditions Remove initial conditions and use reset. |
In the Design Assistant example design, count_q is not reset, which triggers rule RES-30132. Do not assume that Quartus® Prime sets count_q to 0 at power-up.
always@(posedge clk) begin count_q <= count_q + 1'd1; if(count_q == 4'hf) wen_q <= 1'b1; else wen_q <= 1'b0; end
Applying a reset to count_q so that it is set to 0 at reset fixes the violation.
Agilex™ 7 and Intel Stratix 10 devices don’t power up uniformly across all sectors. They power-up sector by sector. Some parts of the device may have their initial conditions before other parts of the device, which can lead to race conditions or spurious writes to memory during power-up.