Timing Closure Rules
Run on the planned snapshot and detect paths with extreme negative slacks. The rules catch any SDC issues that create excessive timing requirements as early as possible.
Look at these rules to save a lot of compilation time on seeds that never pass timing.
- TMC-20001 – Timing Paths with Hold Slack Exceeding threshold
- TMC-20002 – Timing Paths with Removal Slack exceeding threshold
- TMC-20004 – Timing Paths with Setup Slack exceeding Threshold
- TMC-20005 – Timing Paths with Recovery Slack Exceeding Threshold
| Rule | Description | Possible course of action |
|---|---|---|
| TMC-20022 | Incomplete I/O delay assignment | Add the missing options to the delay assignment or modify the clock source |
| TMC-20019 | Partial multicycle assignment | Verify that each setup multicycle assignment has a corresponding hold multicycle assignment and vice versa |
| TMC-20016 | Invalid reference pin | Modify the -reference_pin option of the delay assignment to be the direct fan-out of the clock that you specify in the same assignment |
| TMC-20015 | Inconsistent min/max delay
|
Modify the delay values to ensure that the min delay does not exceed the max delay |
| TMC-20014 | Partial output delay | Verify that output delays have the rise-min, fall-min, rise-max, and fall-max specification |
| TMC-20013 | Partial input delay | Verify that input delays have the rise-min, fall-min, rise-max, and fall-max specification |
| TMC-20012 | Missing output delay | Verify that every output port has an output delay assignment |
| TMC-20011 | Missing input delay | Verify that every input port has an input delay assignment |
| TMC-20052 | Checks for inferred latches in synthesis | Remove any unintended inferred latches from the design |
| TMC-20018 | Latches detected | Remove any unintended inferred latches from the design |
| TMC-20017 | Loops detected | Remove the loops for your design. |