Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide

Document Version Changes
2024.05.15
  • Added Arria® 10 FPGA Development Kit Ordering Information table in Arria® 10 FPGA Development Kit Overview section.
  • Updated Arria® 10 GX Block Diagram figure in General Description section.
  • Updated the upload time in Using the Board Update Portal to Update User Designs section.
  • Updated the figures in the following sections:
    • Arria® 10 GX Block Diagram, Overview of the Development Board Features (ES Edition), Overview of the Development Board Features figures in General Description section.
    • Board Test System GUI figure in Board Test System section.
    • Configure Tab Version Selector Option and Version Selector figures in Version Selector section.
    • The Configure Menu figure in The Configure Menu section.
    • The System Info Tab figure in The System Info Tab section.
    • The GPIO Tab figure in The GPIO Tab section.
    • The Flash Tab figure in The Flash Tab section.
    • The XCVR Status and The XCVR Tab, and Set PMA Values Window figures in The XCVR Tab section.
    • The PCIe® Tab and The PCIe® Status figure in The PCIe® Tab section.
    • The FMC A Status and The FMC A Tab figure in The FMC A Tab section.
    • The FMC B Tab figure in The FMC B Tab section.
    • The DDR3 Tab figure in The DDR3 Tab section.
    • The DDR4 Tab figure in The DDR4 Tab section.
    • Power Monitor Interface figure in The Power Monitor section.
    • Si570(X3) Tab, Si5338(U26) Tab, and Si5338(U14) Tab figures in The Clock Controller section.
2024.01.13
  • Rebranded the product names to Arria® 10 and Quartus® Prime software.
  • Minor text edits.
2023.07.12
  • Retitled the document from Arria 10 FPGA Development Kit User Guide to Arria® 10 FPGA Development Kit User Guide.
  • Minor text edits.
2023.07.11 Updated the supported I/O standard for X1 and X2 in Table: On-Board Oscillators.
2021.03.19 Updated Board Overview [J14 - DDR4 memory (x72) 1200 MHz]
2017.09.21 Updated contents of FACTORY switch in SW6 DIP Switch Default Settings Table in Default Switch and Jumper Settings.
2017.08.08 Added a Caution note to Handling the Board.
2017.07.25
  • Updated FMC of Board Components.
  • Changed all 1.4V PCML I/O Standard to "High Speed Differential I/O" throughout the User Guide.
  • Updated Development Kit Package section to remove references to installer.
2016.05.02
  • Added "Programming the Flash Using Quartus Programmer" section.
  • Updated the Arria 10 FPGA Development Kit block diagram.
2016.03.18 Production release.
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