6.7.3. HiLo External Memory Interface

Arria® 10 FPGA Development Kit User Guide

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Date 5/15/2024

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6.7.3. HiLo External Memory Interface

This section describes the Arria® 10 GX FPGA development board’s external memory interface support and also their signal names, types, and connectivity relative to the Arria® 10 GX FPGA.

The HiLo connector supports plugins the following memory interfaces:

DDR3 x72 (included in the kit)
DDR4 x72 (included in the kit)
RLDRAM3 x36 (included in the kit)
QDR IV x36 (not included. Contact your local Altera sales representative for ordering and availability)

Table 33. HiLo EMI Pin Assignments, Schematic Signal Names
Board Reference	Schematic Signal Name	FPGA Pin Number	I/O Standard
F1	MEM_ADDR_CMD0	M32	1.5 V
H1	MEM_ADDR_CMD1	L32	1.5 V
F2	MEM_ADDR_CMD2	N34	1.5 V
G2	MEM_ADDR_CMD3	M35	1.5 V
H2	MEM_ADDR_CMD4	L34	1.5 V
J2	MEM_ADDR_CMD5	K34	1.5 V
K2	MEM_ADDR_CMD6	M33	1.5 V
G3	MEM_ADDR_CMD7	L33	1.5 V
J3	MEM_ADDR_CMD8	J33	1.5 V
L3	MEM_ADDR_CMD9	J32	1.5 V
E4	MEM_ADDR_CMD10	H31	1.5 V
F4	MEM_ADDR_CMD11	J31	1.5 V
G4	MEM_ADDR_CMD12	H34	1.5 V
H4	MEM_ADDR_CMD13	H33	1.5 V
J4	MEM_ADDR_CMD14	G32	1.5 V
K4	MEM_ADDR_CMD15	E32	1.5 V
M1	MEM_ADDR_CMD16	F33	1.5 V
M2	MEM_ADDR_CMD17	G35	1.5 V
N2	MEM_ADDR_CMD18	H35	1.5 V
L4	MEM_ADDR_CMD19	G33	1.5 V
P5	MEM_ADDR_CMD20	U33	1.5 V
M5	MEM_ADDR_CMD21	T33	1.5 V
P1	MEM_ADDR_CMD22	R34	1.5 V
R4	MEM_ADDR_CMD23	P34	1.5 V
M4	MEM_ADDR_CMD24	N33	1.5 V
R3	MEM_ADDR_CMD25	P33	1.5 V
L2	MEM_ADDR_CMD26	F32	1.5 V
K1	MEM_ADDR_CMD27	T35	1.5 V
P2	MEM_ADDR_CMD28	T34	1.5 V
N4	MEM_ADDR_CMD29	E35	1.5 V
P4	MEM_ADDR_CMD30	U32	1.5 V
N3	MEM_ADDR_CMD31	T32	1.5 V
V2	MEM_CLK_N	R31	1.5 V
V1	MEM_CLK_P	R30	1.5 V
B10	MEM_DMA0	E26	1.5 V
C4	MEM_DMA1	G27	1.5 V
B17	MEM_DMA2	A29	1.5 V
F17	MEM_DMA3	F30	1.5 V
M16	MEM_DMB0	AB32	1.5 V
U16	MEM_DMB1	AG31	1.5 V
U11	MEM_DMB2	Y35	1.5 V
U6	MEM_DMB3	AC34	1.5 V
R6	MEM_DQ_ADDR_CMD0	A32	1.5 V
T1	MEM_DQ_ADDR_CMD1	A33	1.5 V
R2	MEM_DQ_ADDR_CMD2	B32	1.5 V
T2	MEM_DQ_ADDR_CMD3	D32	1.5 V
U2	MEM_DQ_ADDR_CMD4	C33	1.5 V
U3	MEM_DQ_ADDR_CMD5	B33	1.5 V
T4	MEM_DQ_ADDR_CMD6	D34	1.5 V
U4	MEM_DQ_ADDR_CMD7	C35	1.5 V
T5	MEM_DQ_ADDR_CMD8	E34	1.5 V
A4	MEM_DQA0	B28	1.5 V
B4	MEM_DQA1	A28	1.5 V
B5	MEM_DQA2	A27	1.5 V
B6	MEM_DQA3	B27	1.5 V
A8	MEM_DQA4	D27	1.5 V
B8	MEM_DQA5	E27	1.5 V
B9	MEM_DQA6	D26	1.5 V
A10	MEM_DQA7	D28	1.5 V
B1	MEM_DQA8	G25	1.5 V
B2	MEM_DQA9	H25	1.5 V
C2	MEM_DQA10	G26	1.5 V
C3	MEM_DQA11	H26	1.5 V
E3	MEM_DQA12	G28	1.5 V
D4	MEM_DQA13	F27	1.5 V
D1	MEM_DQA14	K27	1.5 V
D2	MEM_DQA15	F28	1.5 V
A12	MEM_DQA16	D31	1.5 V
B12	MEM_DQA17	E31	1.5 V
B13	MEM_DQA18	B31	1.5 V
B14	MEM_DQA19	C31	1.5 V
C15	MEM_DQA20	A30	1.5 V
A16	MEM_DQA21	E30	1.5 V
B16	MEM_DQA22	B30	1.5 V
A18	MEM_DQA23	D29	1.5 V
C16	MEM_DQA24	K30	1.5 V
D16	MEM_DQA25	H30	1.5 V
E16	MEM_DQA26	G30	1.5 V
F16	MEM_DQA27	K31	1.5 V
D17	MEM_DQA28	H29	1.5 V
C18	MEM_DQA29	K29	1.5 V
D18	MEM_DQA30	J29	1.5 V
E18	MEM_DQA31	F29	1.5 V
E2	MEM_DQA32	J28	1.5 V
G16	MEM_DQA33	G31	1.5 V
H16	MEM_DQB0	AC31	1.5 V
J16	MEM_DQB1	AB31	1.5 V
K16	MEM_DQB2	W31	1.5 V
L16	MEM_DQB3	Y31	1.5 V
H17	MEM_DQB4	AD31	1.5 V
K17	MEM_DQB5	AD32	1.5 V
K18	MEM_DQB6	AD33	1.5 V
L18	MEM_DQB7	AA30	1.5 V
M17	MEM_DQB8	AE31	1.5 V
N18	MEM_DQB9	AE32	1.5 V
P17	MEM_DQB10	AE30	1.5 V
P18	MEM_DQB11	AF30	1.5 V
R18	MEM_DQB12	AG33	1.5 V
T16	MEM_DQB13	AG32	1.5 V
T17	MEM_DQB14	AH33	1.5 V
T18	MEM_DQB15	AH31	1.5 V
U15	MEM_DQB16	U31	1.5 V
T14	MEM_DQB17	W33	1.5 V
U14	MEM_DQB18	W32	1.5 V
V14	MEM_DQB19	V31	1.5 V
T13	MEM_DQB20	Y34	1.5 V
T12	MEM_DQB21	W35	1.5 V
U12	MEM_DQB22	W34	1.5 V
V12	MEM_DQB23	V34	1.5 V
T10	MEM_DQB24	AH35	1.5 V
U10	MEM_DQB25	AJ34	1.5 V
V10	MEM_DQB26	AJ33	1.5 V
T9	MEM_DQB27	AH34	1.5 V
T8	MEM_DQB28	AD35	1.5 V
U8	MEM_DQB29	AE34	1.5 V
U7	MEM_DQB30	AC33	1.5 V
V6	MEM_DQB31	AD34	1.5 V
R16	MEM_DQB32	AF32	1.5 V
T6	MEM_DQB33	AB33	1.5 V
V5	MEM_DQS_ADDR_CMD_N	C34	1.5 V
V4	MEM_DQS_ADDR_CMD_P	D33	1.5 V
A7	MEM_DQSA_N0	C26	1.5 V
A3	MEM_DQSA_N1	J27	1.5 V
A15	MEM_DQSA_N2	C29	1.5 V
G18	MEM_DQSA_N3	L29	1.5 V
A6	MEM_DQSA_P0	B26	1.5 V
A2	MEM_DQSA_P1	H28	1.5 V
A14	MEM_DQSA_P2	C30	1.5 V
F18	MEM_DQSA_P3	L30	1.5 V
J18	MEM_DQSB_N0	AA32	1.5 V
V18	MEM_DQSB_N1	AJ31	1.5 V
V17	MEM_DQSB_N2	AA33	1.5 V
V9	MEM_DQSB_N3	AF34	1.5 V
H18	MEM_DQSB_P0	Y32	1.5 V
U18	MEM_DQSB_P1	AJ32	1.5 V
V16	MEM_DQSB_P2	AA34	1.5 V
V8	MEM_DQSB_P3	AF33	1.5 V
A11	MEM_QKA_P0	C28	1.5 V
B18	MEM_QKA_P1	E29	1.5 V
M18	MEM_QKB_P0	Y30	1.5 V
V13	MEM_QKB_P1	V33	1.5 V
H14	MEM_VREF	AB30	—
J13	MEM_VREF	K32	—
K14	MEM_VREF	R32	—

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Arria® 10 FPGA Development Kit User Guide

6.7.3. HiLo External Memory Interface