Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.8.1. Flash

The Arria® 10 GX FPGA development board supports two 1 Gb CFI-compatible synchronous flash devices for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. These devices are part of the shared FM bus that connects to the flash memory and MAX V CPLD EPM2210 System Controller.

Table 42.  Default Memory Map of two 1-Gb CFI Flash Devices
Block Description Size (KB) Address Range
Board test system scratch 512 0x0a10.0000 - 0x0a17.FFFF
User software 14, 336 0x0930.0000 - 0x0A0F.FFFF
Factory software 8, 192 0x08b0.0000 - 0x092F.FFFF
Zips (html, web content) 8, 192 0x0830.0000 -  0x08AF.FFFF
User hardware2 44, 032 0x0580.0000 – 0x082F.FFFF
User hardware1 44, 032 0x02D0.0000 – 0x057F.FFFF
Factory hardware 44, 032 0x0020.0000 – 0x02CF.FFFF
PFL option bits 512 0x0018.0000 – 0x001F.FFFF
Board information 512 0x0010.0000 – 0x0017.FFFF
Ethernet option bits 512 0x0008.0000 – 0x000F.FFFF
User design reset vector 512 0x0000.0000 – 0x0007.FFFF
Table 43.  Flash Pin Assignments, Schematic Signal Names, and Functions (Power Solution 1)

Board Reference

Schematic Signal Name

FPGA Pin Number

I/O Standard Description

F6

FLASH_ADVN

BB22

1.8 V

Address valid

B4

FLASH_CEN1

BB23

1.8 V

Chip enable

E6

FLASH_CLK

BB25

1.8 V

Clock

F8

FLASH_OEN

BC26

1.8 V

Output enable

F7

FLASH_RDYBSYN1

AV23

1.8 V

Ready

D4

FLASH_RESETN

BA23

1.8 V

Reset

G8

FLASH_WEN

BD26

1.8 V

Write enable

C6

FLASH_WPN

—

1.8 V

Write protect

A1

FM_A1

AM11

1.8 V

Address bus

B1

FM_A2

AM12

1.8 V

Address bus

C1

FM_A3

AL12

1.8 V

Address bus

D1

FM_A4

AN13

1.8 V

Address bus

D2

FM_A5

AM13

1.8 V

Address bus

A2

FM_A6

AE12

1.8 V

Address bus

C2

FM_A7

AN15

1.8 V

Address bus

A3

FM_A8

AL10

1.8 V

Address bus

B3

FM_A9

AR10

1.8 V

Address bus

C3

FM_A10

AP11

1.8 V

Address bus

D3

FM_A11

AL13

1.8 V

Address bus

C4

FM_A12

AH11

1.8 V

Address bus

A5

FM_A13

AN14

1.8 V

Address bus

B5

FM_A14

AG11

1.8 V

Address bus

C5

FM_A15

AH10

1.8 V

Address bus

D7

FM_A16

AF14

1.8 V

Address bus

D8

FM_A17

AF15

1.8 V

Address bus

A7

FM_A18

AH14

1.8 V

Address bus

B7

FM_A19

AJ12

1.8 V

Address bus

C7

FM_A20

AJ14

1.8 V

Address bus

C8

FM_A21

AH13

1.8 V

Address bus

A8

FM_A22

AG12

1.8 V

Address bus

G1

FM_A23

AJ13

1.8 V

Address bus

H8

FM_A24

AF12

1.8 V

Address bus

B6

FM_A25

AK14

1.8 V

Address bus

B8

FM_A26

AK11

1.8 V

Address bus

F2

FM_D16

AT25

1.8 V

Data bus

E2

FM_D17

BA19

1.8 V

Data bus

G3

FM_D18

BA20

1.8 V

Data bus

E4

FM_D19

AP24

1.8 V

Data bus

E5

FM_D20

AP23

1.8 V

Data bus

G5

FM_D21

BA18

1.8 V

Data bus

G6

FM_D22

AT24

1.8 V

Data bus

H7

FM_D23

BD19

1.8 V

Data bus

E1

FM_D24

AU23

1.8 V

Data bus

E3

FM_D25

AR24

1.8 V

Data bus

F3

FM_D26

AT23

1.8 V

Data bus

F4

FM_D27

AR25

1.8 V

Data bus

F5

FM_D28

AP22

1.8 V

Data bus

H5

FM_D29

BC19

1.8 V

Data bus

G7

FM_D30

AU22

1.8 V

Data bus

E7

FM_D31

BA17

1.8 V

Data bus
Table 44.  Flash Pin Assignments, Schematic Signal Names, and Functions (Power Solution 2)
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
__ FLASH_ADVN BC25 1.8 V Address valid
F2 FLASH_CEN1 BB23 1.8 V Chip enable
__ FLASH2_CLK BB25 1.8 V Clock
G2 FLASH_OEN BC26 1.8 V Output enable
A4 FLASH_RDYBSYN1 AV23 1.8 V Ready
B5 FLASH_RESETN BA23 1.8 V Reset
A5 FLASH_WEN BD26 1.8 V Write enable
B4 FLASH_WPN — 1.8 V Write protect
E2 FM_A1 AM11 1.8 V Address bus
D2 FM_A2 AM12 1.8 V Address bus
C2 FM_A3 AL12 1.8 V Address bus
A2 FM_A4 AN13 1.8 V Address bus
B2 FM_A5 AM13 1.8 V Address bus
D3 FM_A6 AE12 1.8 V Address bus
C3 FM_A7 AN15 1.8 V Address bus
A3 FM_A8 AL10 1.8 V Address bus
B6 FM_A9 AR10 1.8 V Address bus
A6 FM_A10 AP11 1.8 V Address bus
C6 FM_A11 AL13 1.8 V Address bus
D6 FM_A12 AH11 1.8 V Address bus
B7 FM_A13 AN14 1.8 V Address bus
A7 FM_A14 AG11 1.8 V Address bus
C7 FM_A15 AH10 1.8 V Address bus
D7 FM_A16 AF14 1.8 V Address bus
E7 FM_A17 AF15 1.8 V Address bus
B3 FM_A18 AH14 1.8 V Address bus
C4 FM_A19 AJ12 1.8 V Address bus
D5 FM_A20 AJ14 1.8 V Address bus
D4 FM_A21 AH13 1.8 V Address bus
C5 FM_A22 AG12 1.8 V Address bus
B8 FM_A23 AJ13 1.8 V Address bus
C8 FM_A24 AF12 1.8 V Address bus
F8 FM_A25 AK14 1.8 V Address bus
G8 FM_A26 AK11 1.8 V Address bus
E3 FM_D16 AT25 1.8 V Data bus
H3 FM_D17 BA19 1.8 V Data bus
E4 FM_D18 BA20 1.8 V Data bus
H4 FM_D19 AP24 1.8 V Data bus
H5 FM_D20 AP23 1.8 V Data bus
E5 FM_D21 BA18 1.8 V Data bus
H6 FM_D22 AT24 1.8 V Data bus
E6 FM_D23 BD19 1.8 V Data bus
F3 FM_D24 AU23 1.8 V Data bus
G3 FM_D25 AR24 1.8 V Data bus
F4 FM_D26 AT23 1.8 V Data bus
G4 FM_D27 AR25 1.8 V Data bus
F5 FM_D28 AP22 1.8 V Data bus
G6 FM_D29 BC19 1.8 V Data bus
F6 FM_D30 AU22 1.8 V Data bus
G7 FM_D31 BA17 1.8 V Data bus
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