AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)

Following are the guidelines for the application logic when using the compact packing scheme:
  • For a given clock cycle, the header always starts from segment 0, or on the following segment after the end of the previous packet. The header for segment 1 is allowed depending on the utilization for segment 0. Refer to the table below for the allowed conditions. Note that the table does not include all the signals for the AXI-ST RX interface. It only shows the Header (H) and Data (D) combinations to highlight the valid cases where a TLP can be started on segment 1.
  • When sending multiple packets on multiple segments in a single clock cycle, the headers are placed on contiguous segments starting with segment 0. For example, when using a 1024-bit data bus with 4 segments, the header can be on segments 0, 1, 2 but not on segments 0, 1, 3 nor on segments 1, 2, 3.
The following table describes the possible combinations across segments:
Table 38.  RX AXI-ST Compact Packing Scheme with a 512-Bit Tdata Bus (Gen4x16 P-Tile - 512 Bits, 2 Segments x 256 Bits Wide)
S0 S1
H, D H, D
H, D D
D H, D

Example of the compact packing scheme in Gen4x16 with a 512-bit, 2-segment bus on the RX AXI-ST Interface:

1st Command with Data - Payload 16 Bytes

2nd Command with Data - Payload 32 Bytes

3rd Command with Data - Payload 96 Bytes

4th Command with Data – Payload 20 Bytes