Visible to Intel only — GUID: lrs1700067334773
Ixiasoft
Visible to Intel only — GUID: lrs1700067334773
Ixiasoft
6.10. Control and Status Register Responder Interface (lite_csr)
The IP provides a Control and Status Register Interface to access registers implemented in its modules. You can access PCI/PCIe Configuration Registers of all Functions through this interface as well as SS soft register space registers implemented in design. The interface follows AXI4-Lite protocol.
The IP does not differentiate between non-secure and secure accesses. All accesses are considered secure.
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
Write Address Channel | |||
app_ss_lite_csr_awvalid | Input | axi_lite_clk | Indicates that the write address channel signals are valid. |
ss_app_lite_csr_awready | Output | axi_lite_clk | Indicates that a transfer on the write address channel can be accepted. |
app_ss_lite_csr_awaddr[LiteSlvAWD-1:0] | Input | axi_lite_clk | The address of the first transfer in a write transaction. The default value of LiteSlvAWD = 18 |
Write Data Channel | |||
app_ss_lite_csr_wvalid | Input | axi_lite_clk | Indicates that the write data channel signals are valid. |
ss_app_lite_csr_wready | Output | axi_lite_clk | Indicates that a transfer on the write data channel can be accepted. |
app_ss_lite_csr _wdata[LiteSlvDWD-1:0] | Input | axi_lite_clk | Write Data The default value of LiteSlvDWD=32 |
app_ss_lite_csr_wstrb[LiteSlvDWD/8-1:0] | Input | axi_lite_clk | Write strobes, indicate which byte lanes hold valid data. |
Write Response Channel | |||
ss_app_lite_csr_bvalid | Output | axi_lite_clk | Indicates that the write response channel signals are valid. |
app_ss_lite_csr_bready | Input | axi_lite_clk | Indicates that a transfer on the write response channel can be accepted. |
ss_app_lite_csr_bresp[1:0] | Output | axi_lite_clk | Write response, indicates the status of a write transaction. |
Read Address Channel | |||
app_ss_lite_csr_arvalid | Input | axi_lite_clk | Indicates that the read address channel signals are valid. |
ss_app_lite_csr_arready | Output | axi_lite_clk | Indicates that a transfer on the read address channel can be accepted. |
app_ss_lite_csr_araddr[LiteSlvAWD-1:0] | Input | axi_lite_clk | The address of the first transfer in a read transaction. The default value of LiteSlvAWD = 18 |
Read Data Channel | |||
ss_app_lite_csr_rvalid | Output | axi_lite_clk | Indicates that the read data channel signals are valid. |
app_ss_lite_csr_rready | Input | axi_lite_clk | Indicates that a transfer on the read data channel can be accepted. |
ss_app_lite_csr_rdata[LiteSlvDWD:0] | Output | axi_lite_clk | Read data The default value of LiteSlvDWD=32 |
ss_app_lite_csr_rresp[1:0] | Output | axi_lite_clk | Read response, indicates the status of a read transfer. |