AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

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Document Table of Contents

6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles)

Below is a figure that shows the possible header positions in the simple packing scheme for 1024-, 512- and 256-bit wide data buses.

Example of the simple packing scheme in Gen5x16 with a 1024-bit, 4-segment bus on the TX AXI-ST Interface:

1st Command with Data - Payload 16 Bytes

2nd Command with Data - Payload 64 Bytes

3rd Command with Data - Payload 128 Bytes

4th Command with Data - Payload 60 Bytes

5th Command with Data - Payload 32 Bytes

6th Command without Data