Visible to Intel only — GUID: vxn1700108963883
Ixiasoft
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
1.3. What is PCI Express* ?
1.4. What are the Intel® FPGA IPs for PCI Express* ?
1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ?
1.6. Example Use Models
1.7. Design Flow Requirements
3.1. Download and Install Quartus Software
3.2. Obtain and Install Intel FPGA IPs and Licenses
3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express*
3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces
3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.6. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.9. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
4.1. Clocks and Resets
4.2. PCIe Hard IP (HIP)
4.3. HIP Interface (IF) Adaptor
4.4. Application Error Reporting
4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface
4.6. Configuration Space Extension
4.7. Control Shadow
4.8. Configuration Intercept Interface
4.9. Power Management
4.10. Legacy Interrupt
4.11. Credit Handling
4.12. Completion Timeout
4.13. Transaction Ordering
4.14. Page Request Service (PRS) Events
4.15. TX Non-Posted Metering Requirement on Application
4.16. MSI Pending
4.17. D-State Status
4.18. Configuration Retry Status Enable
4.19. AXI-Streaming Interface
4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
6.1. Overview
6.2. Clocks and Resets
6.3. Application Packet Interface
6.4. Configuration Extension Bus Interface
6.5. Configuration Intercept Interface
6.6. Function Level Reset Interface
6.7. Control Shadow Interface (st_ctrlshadow)
6.8. Completion Timeout Interface (st_cplto)
6.9. Miscellaneous Signals
6.10. Control and Status Register Responder Interface (lite_csr)
6.11. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg)
6.12. VIRTIO PCI* Configuration Access Interface
6.13. Serial Data Signals
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version
7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features
7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes
7.3.1.4. ERROR GEN CTRL
7.3.1.5. ERROR GEN ATTR
7.3.1.6. ERROR TLP Header DW0-3
7.3.1.7. ERROR TLP Prefix
7.3.1.8. HOT PLUG GEN CTRL
7.3.1.9. POWER MANAGEMENT CTRL
7.3.1.10. LEGACY INTERRUPT CTRL
7.3.1.11. CFG REG IA CTRL
7.3.1.12. CFG REG IA FN NUM
7.3.1.13. CFG REG IA WRDATA
7.3.1.14. CFG REG IA RDDATA
7.3.1.15. PRS CTRL
7.3.1.16. MSI PENDING CTRL
7.3.1.17. MSI PENDING
7.3.1.18. D-STATE STS
7.3.1.19. CFG RETRY CTRL
7.3.3.1. PERFMON CTRL
7.3.3.2. TX MRD TLP
7.3.3.3. TX MWR TLP
7.3.3.4. TX MSG TLP
7.3.3.5. TX CFGWR TLP
7.3.3.6. TX CFGRD TLP
7.3.3.7. RX MRD TLP
7.3.3.8. RX MWR TLP
7.3.3.9. RX MSG TLP
7.3.3.10. RX CFGWR TLP
7.3.3.11. RX CFGRD TLP
7.3.3.12. TX MEM DATA
7.3.3.13. TX CPL DATA
7.3.3.14. RX MEM DATA
7.3.3.15. RX CPL DATA
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Ixiasoft
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers
The following table lists the control registers implemented by the IP. The IP Control registers start from Base Address = 0x0.
Register Name | Offset |
---|---|
IP Version | 0x0000_0000 |
IP Features | 0x0000_0004 |
IP Interface Attributes | 0x0000_0008 |
Reserved | 0x0000_000C |
ERROR GEN CTRL | 0x0000_0010 |
ERROR GEN ATTR | 0x0000_0014 |
ERROR TLP Header DW0 | 0x0000_0018 |
ERROR TLP Header DW1 | 0x0000_001C |
ERROR TLP Header DW2 | 0x0000_0020 |
ERROR TLP Header DW3 | 0x0000_0024 |
ERROR TLP Prefix | 0x0000_0028 |
Hot Plug Gen Control | 0x0000_002C |
Power Management Control | 0x0000_0030 |
Legacy Interrupt Control | 0x0000_0034 |
CFG REG IA Control | 0x0000_00C8 |
CFG REG IA FN NUM | 0x0000_00CC |
CFG REG IA FN WRDATA | 0x0000_00D0 |
CFG REG IA FN RDDATA | 0x0000_00D4 |
PRS Control | 0x0000_00D8 |
MSI Pending Control | 0x0000_00DC |
MSI Pending | 0x0000_00E0 |
D-State STS | 0x0000_00E4 |
CFG Retry Control | 0x0000_00E8 |
Section Content
AXI Streaming Intel FPGA IP for PCI Express Version
AXI Streaming Intel FPGA IP for PCI Express Features
AXI Streaming Intel FPGA IP for PCI Express Interface Attributes
ERROR GEN CTRL
ERROR GEN ATTR
ERROR TLP Header DW0-3
ERROR TLP Prefix
HOT PLUG GEN CTRL
POWER MANAGEMENT CTRL
LEGACY INTERRUPT CTRL
CFG REG IA CTRL
CFG REG IA FN NUM
CFG REG IA WRDATA
CFG REG IA RDDATA
PRS CTRL
MSI PENDING CTRL
MSI PENDING
D-STATE STS
CFG RETRY CTRL