AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 790711
Date 2/12/2024
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* 4. IP Architecture and Functional Description 5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters 6. Interfaces and Signals 7. Register Descriptions 8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Specifications B. Simulating the Design Example
1. Introduction x
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. What is PCI Express* ? 1.4. What are the Intel® FPGA IPs for PCI Express* ? 1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ? 1.6. Example Use Models 1.7. Design Flow Requirements
1.7. Design Flow Requirements x
1.7.1. Design Software 1.7.2. Hardware
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Performance
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* x
3.1. Download and Install Quartus Software 3.2. Obtain and Install Intel FPGA IPs and Licenses 3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express* 3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces 3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.6. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.9. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces x
3.4.1. Clocking and Resets 3.4.2. Application Packet Datapath 3.4.3. Enabling Additional Features 3.4.4. Enabling Optional Interfaces
3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.5.1. Simulating the Design Example
3.5.1. Simulating the Design Example x
3.5.1.1. Steps to Run Simulations
3.5.1.1. Steps to Run Simulations x
3.5.1.1.1. VCS* Simulator
3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.7.1. Installing the Linux Kernel Driver
3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.8.1. Running the Design Example
3.8.1. Running the Design Example x
3.8.1.1. Running the PIO Design Example
3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.10.1. Debugging Link Training Issues 3.10.2. Debugging Data Transfer and Performance Issues
3.10.1. Debugging Link Training Issues x
3.10.1.1. Operating System Tools and Utilities 3.10.1.2. Signal Tap Logic Analyzer 3.10.1.3. Additional Debug Tools
3.10.2. Debugging Data Transfer and Performance Issues x
3.10.2.1. Advanced Error Reporting (AER) 3.10.2.2. Second-Level Debug Tools
4. IP Architecture and Functional Description x
4.1. Clocks and Resets 4.2. PCIe Hard IP (HIP) 4.3. HIP Interface (IF) Adaptor 4.4. Application Error Reporting 4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface 4.6. Configuration Space Extension 4.7. Control Shadow 4.8. Configuration Intercept Interface 4.9. Power Management 4.10. Legacy Interrupt 4.11. Credit Handling 4.12. Completion Timeout 4.13. Transaction Ordering 4.14. Page Request Service (PRS) Events 4.15. TX Non-Posted Metering Requirement on Application 4.16. MSI Pending 4.17. D-State Status 4.18. Configuration Retry Status Enable 4.19. AXI-Streaming Interface 4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters x
5.1. Parameter Editor Parameters
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. Application Packet Interface 6.4. Configuration Extension Bus Interface 6.5. Configuration Intercept Interface 6.6. Function Level Reset Interface 6.7. Control Shadow Interface (st_ctrlshadow) 6.8. Completion Timeout Interface (st_cplto) 6.9. Miscellaneous Signals 6.10. Control and Status Register Responder Interface (lite_csr) 6.11. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg) 6.12. VIRTIO PCI* Configuration Access Interface 6.13. Serial Data Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. Application Packet Interface x
6.3.1. Header Format 6.3.2. Prefix Format 6.3.3. Function Number Format 6.3.4. BAR Number Format 6.3.5. Data and Header Packing Schemes 6.3.6. Application Packet Transmit Interface (st_tx) 6.3.7. Application Packet Receive Interface (st_rx) 6.3.8. Flow Control Credit Handling
6.3.5. Data and Header Packing Schemes x
6.3.5.1. HIP Native Mode Packing 6.3.5.2. Compact Packing 6.3.5.3. Simple Packing
6.3.5.1. HIP Native Mode Packing x
6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) 6.3.5.1.2. Application Logic Guidelines for the AXI Streaming RX Interface in HIP Native Mode
6.3.5.2. Compact Packing x
6.3.5.2.1. Application Logic Guidelines for the AXI Streaming TX Interface in Compact Mode (P/R-Tiles) 6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)
6.3.5.3. Simple Packing x
6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles) 6.3.5.3.2. Application Logic Guidelines for the AXI Streaming RX Interface in Simple Mode (P/R-Tiles)
6.3.8. Flow Control Credit Handling x
6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt) 6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)
6.4. Configuration Extension Bus Interface x
6.4.1. Configuration Extension Bus Request Interface (st_cebreq) 6.4.2. Configuration Extension Bus Response Interface (st_cebresp)
6.5. Configuration Intercept Interface x
6.5.1. Configuration Intercept Request Interface (st_ciireq) 6.5.2. Configuration Intercept Response Interface (st_ciiresp)
6.6. Function Level Reset Interface x
6.6.1. Function Level Reset Received Interface (st_flrrcvd) 6.6.2. Function Level Reset Completion Interface (st_flrcmpl)
6.12. VIRTIO PCI* Configuration Access Interface x
6.12.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq) 6.12.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)
7. Register Descriptions x
7.1. Register Address Map 7.2. PCIe Configuration Space 7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map
7.2. PCIe Configuration Space x
7.2.1. PCIe Configuration Space Registers
7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map x
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers 7.3.2. IP Debug Registers 7.3.3. IP Performance Monitor Registers
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers x
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version 7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features 7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes 7.3.1.4. ERROR GEN CTRL 7.3.1.5. ERROR GEN ATTR 7.3.1.6. ERROR TLP Header DW0-3 7.3.1.7. ERROR TLP Prefix 7.3.1.8. HOT PLUG GEN CTRL 7.3.1.9. POWER MANAGEMENT CTRL 7.3.1.10. LEGACY INTERRUPT CTRL 7.3.1.11. CFG REG IA CTRL 7.3.1.12. CFG REG IA FN NUM 7.3.1.13. CFG REG IA WRDATA 7.3.1.14. CFG REG IA RDDATA 7.3.1.15. PRS CTRL 7.3.1.16. MSI PENDING CTRL 7.3.1.17. MSI PENDING 7.3.1.18. D-STATE STS 7.3.1.19. CFG RETRY CTRL
7.3.2. IP Debug Registers x
7.3.2.1. HIP Status 7.3.2.2. HIP BP CYCLES 7.3.2.3. HIA BP CYCLES 7.3.2.4. APP BP CYCLES 7.3.2.5. HIA RX BP CYCLES
7.3.3. IP Performance Monitor Registers x
7.3.3.1. PERFMON CTRL 7.3.3.2. TX MRD TLP 7.3.3.3. TX MWR TLP 7.3.3.4. TX MSG TLP 7.3.3.5. TX CFGWR TLP 7.3.3.6. TX CFGRD TLP 7.3.3.7. RX MRD TLP 7.3.3.8. RX MWR TLP 7.3.3.9. RX MSG TLP 7.3.3.10. RX CFGWR TLP 7.3.3.11. RX CFGRD TLP 7.3.3.12. TX MEM DATA 7.3.3.13. TX CPL DATA 7.3.3.14. RX MEM DATA 7.3.3.15. RX CPL DATA
A. Specifications x
A.1. P-Tile Specifications A.2. F-Tile Specifications A.3. R-Tile Specifications
A.1. P-Tile Specifications x
A.1.1. P-Tile Completion Buffer Size A.1.2. Power Management A.1.3. MSI and MSI-X
A.2. F-Tile Specifications x
A.2.1. F-Tile Completion Buffer Size A.2.2. Power Management
A.3. R-Tile Specifications x
A.3.1. R-Tile Completion Buffer Size A.3.2. Power Management A.3.3. MSI and MSI-X
B. Simulating the Design Example x
B.1. Testbench
B.1. Testbench x
B.1.1. Testbench Modules B.1.2. Test Driver Module B.1.3. PIO Design Example Testbench B.1.4. Root Port BFM
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example

6.2.2. Interface Reset Signals

Table 26.  Interface Reset Signals
Signal Name Direction Type Description
pin_perst I Asynchronous This is an active-low input to the PCIe Hard IP. It implements the PERST# function defined by the PCIe specification.
p<n>_pin_perst_n where n = 0, 1, 2, 3 O Asynchronous This is the PERST output signal from the Hard IP. It is derived from the pin_perst_n input signal.
p<n>_Subsystem_cold_rst_n I Could be implemented as synchronous or asynchronous reset. IP global reset. Resets sticky register bits. Active low.
p<n>_Subsystem_warm_rst_n I Could be implemented as synchronous or asynchronous reset. IP warm reset. Does not reset sticky register bits. Active low.
p<n>_Subsystem_cold_rst_ack_n O Asynchronous Handshake signal. Indicates cold reset action is completed by the IP.
p<n>_Subsystem_warm_rst_ack_n O Asynchronous Handshake signal. Indicates warm reset action is completed by the IP.
p<n>_axi_st_areset_n I The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of axi_st_clk. AXI-Streaming main datapath reset. Active-LOW reset signal. Used to reset the AXI-ST datapath interface.
p<n>_axi_lite_areset_n I The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of axi_lite_clk. AXI-Lite reset. Active-LOW reset signal. Used to reset the AXI Lite interface.
p<n>_Subsystem_rst_req I Asynchronous

Reset entry indication from Central Reset Sequencer block implemented by the user logic.

p<n>_Subsystem_rst_rdy O Asynchronous Ready signal for reset entry indication from the IP to the Central Reset Sequencer block.
p<n>_initiate_warmrst_req O Asynchronous

Warm Reset entry required indication from the IP block to the Central Reset Sequencer in user logic.

Initiator block cannot issue new reset entry request until previous reset sequence (entire reset operation) is completed.

p<n>_initiate_rst_req_rdy I Asynchronous Indicates the Central Reset Sequencer block in the user logic has accepted the initiation request and will start issuing resets.
p<n>_reset_status_n O Synchronous to coreclkout_hip of Hard IP

Active low signal. When asserted, indicates HARD IP is in reset state. When asserted, will continue to stay asserted until pin perstn is deasserted and HARD IP is out of reset state.

The application logic can use this signal to drive its reset network.

The reset_status_n output of HIP drives this signal.

Note: You must implement the user reset sequencer in your application user logic and follow the assertion and deassertion sequence for graceful entry and exit for each of the resets (cold, warm etc). The following figure shows the reset connections between a user-implemented reset controller and the AXI Streaming Intel® FPGA IP for PCI Express* .
Figure 28. User Reset Controller Connections

The following table indicates the signals/blocks used for each type of reset:

Table 27.  Signals and Blocks Used for Reset Type
Reset Type Signals/Blocks Under Reset
Cold Reset
  • Subsystem_cold_rst_n and Subsystem_warm_rst_n will be asserted
  • Bus resets (AXI-ST/AXI-MM/AXI-Lite) will be asserted
  • HIP will undergo reset

Warm Reset

(e.g., LTSSM Hot reset)
  • Subsystem_cold_rst_n will not be asserted
  • Bus resets (AXI-ST/AXI-MM/AXI-Lite) will be asserted also
  • HIP will undergo reset also

Expected reset isolation requirement for reset domain crossings are shown in the following table.

Table 28.  Reset Isolation Requirement for Reset Domain Crossings
  • No: No reset isolation required for Column->Row Reset Domain Crossing
  • Yes: Reset isolation required for Column->Row Reset Domain Crossing
  • N/A: Not applicable since same Reset Domain Crossing

Column: Source

Row: Destination

 Cold Reset HIP Reset Warm Reset AXI-ST/MM Reset AXI-Lite Reset
Cold Reset N/A No Yes No No
HIP Reset No N/A No No No
Warm Reset No No N/A No No
AXI-ST Reset No No No N/A No
AXI-Lite Reset No No No No N/A
Note: In Endpoint mode, IP warm reset could be asserted without IP cold reset in scenarios such LTSSM Hot Reset.

Cold Reset Entry and Exit Sequence

The following is the sequence for Cold Reset Entry.

  1. Cold reset is initiated by the assertion of Hard IP’s p*_pin_perst_n.
  2. Hard IP asserts pld_link_reset_req to the AXI IP soft logic.
  3. The AXI IP notifies the user reset sequencer by asserting initiate_warmrst_req.
  4. User reset sequencer then asserts _rst_req.
  5. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  6. The AXI IP asserts Subsystem_rst_rdy to user reset sequencer, indicating the IP's internal blocks are ready for reset.
  7. User reset sequencer acknowledges to the AXI IP that it is ready for reset by asserting initiate_rst_req_rdy.
  8. The AXI IP soft logic then asserts pld_warm_rst_rdy to Hard IP.
  9. Hard IP asserts reset_status_n indicating the application logic needs to be in reset.
  10. User reset sequencer asserts Subsystem_cold_rst_n, Subsystem_warm_rst_n and AXI bus resets.
Figure 29. Cold Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

Warm Reset Entry & Exit Sequence

The following is the sequence for Warm Reset Entry.

  1. Warm reset is initiated by the assertion of Hard IP event, e.g., Hot reset.
  2. Hard IP asserts pld_link_reset_req to the AXI IP soft logic.
  3. The AXI IP notifies the user reset sequencer by asserting initiate_warmrst_req.
  4. The user reset sequencer asserts Subsystem_rst_req.
  5. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  6. The AXI IP asserts Subsystem_rst_rdy to the user reset sequencer, indicating the IP's internal blocks are ready for reset.
  7. The user reset sequencer acknowledges to the IP that it is ready for reset by asserting initiate_rst_req_rdy.
  8. The AXI IP soft logic then asserts pld_warm_rst_rdy to Hard IP.
  9. Hard IP asserts reset_status_n indicating the application logic needs to be in reset.
  10. The user reset sequencer asserts Subsystem_warm_rst_n and AXI bus resets.
Note: Warm Reset flow is similar to Cold Reset flow, with the exception that p*_pin_perst_n and Subsystem_cold_rst_n are not asserted for warm reset
Figure 30. Warm Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

User reset sequencer initiated Cold Reset Entry and Exit Sequence

  1. Cold reset is initiated by the user reset sequencer by the assertion of the Subsystem_rst_req.
  2. The AXI IP sequences its internal blocks for reset entry (intA_rst_req, intB_rst_req, intA_rst_rdy, intB_rst_rdy, …).
  3. The AXI IP asserts Subsystem_rst_rdy to user reset sequencer, indicating the IP's internal blocks are ready for reset.
  4. The user reset sequencer asserts Subsystem_cold_rst_n, Subsystem_warm_rst_n and AXI bus resets.
Figure 31. User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.

User reset sequencer triggered Warm Reset flow is the same as the user reset sequencer triggered Cold Reset flow, with the exception that the Subsystem_cold_rst_n will not be asserted for this flow.

Figure 32. User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence Timing Diagram
Note: * indicates the signals between the AXI Streaming Intel® FPGA IP for PCI Express* soft logic and the Hard IP. These signals are not available to the application logic.
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