Embedded Design Handbook

ID 683689
Date 8/28/2023
Public
Document Table of Contents

5.2.6.3.3. Programming

Programming Files Generation

  1. Open the Convert Programming Files… from File menu in Intel® Quartus® Prime software.
  2. Under Output programing file section, set the following items:
    1. Programming file type: Programmer Object File (.pof)
    2. Configuration device: Select according to your CFI flash
    3. Mode: Passive Parallel x8/x16/3222
    4. File name: You may select your preferred path for the output file (.pof). By default this is generated under your project root directory.
    5. Keep the default settings for Create Memory Map File.
    Figure 217. Output programming file Setting
  3. Under Input files to convert section:
    1. Select SOF Data, then Add File… and choose the *.sof file generated by Intel® Quartus® Prime compilation.
    2. Select the added *.sof file, click Properties, then enable Compression and click OK.
    3. Select SOF Data and click Properties. Set the Address mode for selected pages to Start and set the Start address (32-bit hexadecimal), then click OK.
      Figure 218. SOF Data Properties
    4. Click Add Hex Data and select Absolute addressing mode. Browse to the HEX file location and click OK.
      Note: You may select Relative addressing mode if you would like to set a relative address to the reset vector offset you configured earlier.
      Figure 219. Add Hex Data
  4. Click Options/Boot info., set the Option bit address (32-bit hexadecimal).
    Figure 220. Option Bit Address
  5. Click Generate to generate the POF programming file.
    Figure 221. Convert Programming File Settings

CFI Flash Programming

  1. Ensure the MSEL pin setting on your board is configured to Fast Passive Parallel (FPP) x8/x16/32 23.
  2. Open the Intel® Quartus® Prime programmer and make sure JTAG was detected under the Hardware Setup.
  3. Click Auto Detect and select your FPGA device, then click OK.
  4. Right click on the MAX CPLD and click Change File.
  5. Open the PFL *.pof file that contains programming logic.
  6. Check the MAX CPLD including CFM and UFM under Program/Configure.
  7. Click Start to start programming the MAX CPLD.
    Figure 222. Program MAX CPLD with Programming Logic
  8. Click Auto Detect after the programming successful. Click Yes if you are asked to overwrite existing settings.
    Figure 223. Overwrite Existing Settings
  9. The CFI flash device will be attached to the MAX CPLD. Right click on the CFI flash device and click Change File.
  10. Open the generated *.pof file that contains Nios® II application.
  11. Check the CFI flash device including Page_0, HEX file and OPTION_BITS under Program/Configure.\
  12. Click Start to start programming the CFI flash.
    Figure 224. Program CFI Flash
  13. After the programming successful, right click on the MAX CPLD and click Change File.
  14. Open the PFL *.pof file that contains configuration controller logic.
  15. Check the MAX CPLD including CFM and UFM under Program/Configure.
  16. Click Start to start programming the MAX CPLD.
    Figure 225. Program MAX CPLD with Configuration Controller Logic
  17. Power cycle your hardware.
22 Set data width according to the supported scheme.
23 Set data width according to supported scheme.