DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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Document Table of Contents

11.12.2.9. CONTROL (0x64)

Table 248.  CONTROL (0x64)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Go 0 RW Setting this bit to 1 causes the CV2AXI core to start data output on the next video frame boundary. 0x0