DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.3.8. DPTX_TEST_80BIT_PATTERN3/DPTX_TEST_264BIT_PATTERN3

Address: 0x0017

Direction: RW

Reset: 0x00000000

Table 88.  DPTX_TEST_80BIT_PATTERN3 Bits

Bit

Bit Name

Function

31:16

264BIT_PATTERN3

Bits 95:80 of the 264 bit custom pattern for PHY compliance test.

15:0

80BIT_PATTERN3

Bits 79:64 of the 80/264 bit custom pattern for PHY compliance test.

Bits 79:64 of the 264 bit custom pattern for PHY compliance test.