DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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11.5.1. DPRX_BER_TEST_PATTERN

Address: 0x000B

Direction: RW

Reset: 0x00000000

Table 166.  DPRX0_MSA_MVID Bits

Bit

Bit Name

Function

31

Unused

30:24

PATT3

Pattern selection for lane 3:

  • 00h = No test pattern (normal mode)
  • 03h = PRBS7
  • 08h = 128b/132b_TPS1 test pattern (Nyquist)
  • 10h = 128b/132b_TPS2 test pattern
  • 18h = PRBS9
  • 20h = PRBS11
  • 28h = PRBS15
  • 30h = PRBS23
  • 38h = PRBS31
  • 40h = 264 bit custom pattern
  • 48h = SQnum - Square pattern of num 1s, followed by num 0s

23

Unused  

22:16

PATT2

Pattern selection for lane 2:

  • 00h = No test pattern (normal mode)
  • 03h = PRBS7
  • 08h = 128b/132b_TPS1 test pattern (Nyquist)
  • 10h = 128b/132b_TPS test pattern
  • 18h = PRBS9
  • 20h = PRBS11
  • 28h = PRBS15
  • 30h = PRBS23
  • 38h = PRBS31
  • 40h = 264 bit custom pattern
  • 48h = SQnum - Square pattern of num 1s, followed by num 0s

15

Unused  
14:8 PATT1

Pattern selection for lane 1:

  • 00h = No test pattern (normal mode)
  • 03h = PRBS7
  • 08h = 128b/132b_TPS1 test pattern (Nyquist)
  • 10h = 128b/132b_TPS2 test pattern
  • 18h = PRBS9
  • 20h = PRBS11
  • 28h = PRBS15
  • 30h = PRBS23
  • 38h = PRBS31
  • 40h = 264 bit custom pattern
  • 48h = SQnum - Square pattern of num 1s, followed by num 0s
7 Unused  
6:0 PATT0

Pattern selection for lane 0:

  • 00h = No test pattern (normal mode)
  • 03h = PRBS7
  • 08h = 128b/132b_TPS1 test pattern (Nyquist)
  • 10h = 128b/132b_TPS test pattern
  • 18h = PRBS9
  • 20h = PRBS11
  • 28h = PRBS15
  • 30h = PRBS23
  • 38h = PRBS31
  • 40h = 264 bit custom pattern
  • 48h = SQnum - Square pattern of num 1s, followed by num 0s