DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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5.8.3.1. Video Interface (TX Video IM Enable = 0)

If you do not enable the video image interface feature, the core uses the traditional HSYNC/VSYNC/DE video input interface (txN_video_in).

You specify the data input width through the Maximum video input color depth parameter. The same input port transfers RGB and YCbCr data in 4:4:4, 4:2:2, or 4:2:0 color format. Data is most-significant bit aligned.

Figure 18. Video Input Data Format18 bpp to 48 bpp for RGB/YCbCr 4:4:4, 16 bpp to 32 bpp for YCbCr 4:2:2, and 12 bpp to 24 bpp for YCbCr 4:2:0 port width when txN_video_in port width is 48 (Maximum video input color depth = 16 bpc, Pixel input mode = Single)
Table 33.  Video Ports for 4:2:2 and 4:2:0 Color Formats
Color Format Description
Sub-sampled 4:2:2 color format
  • Video port bits 47:32 are unused
  • Video port bits 31:16 always transfer the Y component
  • Video port bits 15:0 always transfer the alternate Cb or Cr component
Sub-sampled 4:2:0 color format
  • For even lines (starting with line 0)
    • Video port bits 47:32 always transfer the Yn+1 component.
    • Video port bits 31:16 always transfer the Yn component.
    • Video port bits 15:0 always transfer the Cbn component.
  • For odd lines
    • Video port bits 47:32 always transfer the Yn+1 component.
    • Video port bits 31:16 always transfer the Yn component.
    • Video port bits 15:0 always transfer the Crn component.
Note: The frequency of txN_vid_clk must be halved when YCbCr 4:2:0 is used because two pixels are fed into a single clock cycle.
Table 34.  YCbCr 4:2:0 Input Data Ordering Compared to RGB 4:4:4
Pixel Indexes R Position G Position B Position

0 and 1

Y1

Y0

  • Cb0 (Even lines)
  • Cr0 (Odd lines)

2 and 3

Y3

Y2

  • Cb2 (Even lines)
  • Cr2 (Odd lines)

4 and 5

Y5

Y4

  • Cb4 (Even lines)
  • Cr4 (Odd lines)
... ... ... ...

If you set Pixel input mode to Dual or Quad, the IP sends two or four pixels in parallel, respectively. To support video resolutions with horizontal active, front porch, or back porch of a length not divisible by 2 or 4, the data enable, horizontal sync, and vertical sync signals are widened.

The following figure shows the pixel data order from the least significant bits to the most significant bits.

Figure 19. Video Input Data AlignmentFor RGB 18 bpp when txN_video_in port width is 96 (Maximum video input color depth = 8 bpc, Pixel input mode = Quad).