External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.2.9. ac_parity_err for DDR4

Table 57.  Interface: ac_parity_errInterface type: Conduit
Port Name Direction Description
ac_parity_err Output PORT_AC_PARITY_STATE_DESC