External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.4.17. sideband11

address=54(32 bit)

Field Bit High Bit Low Description Access
mmr_auto_pd_ack 0 0 Auto Power Down In Progress. Acknowledgement signal for auto power down. A value of 1 indicates that the memory is in auto power down mode. Read