External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.3.4. pll_locked for QDR II/II+/II+ Xtreme

PLL locked signal

Table 90.  Interface: pll_lockedInterface type: Conduit
Port Name Direction Description
pll_locked Output PLL lock signal to indicate whether the PLL has locked