External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.16. emif_usr_reset_n for DDR3

User clock domain reset interface

Table 27.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion