External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.34. hps_emif for DDR3

Conduit between Hard Processor Subsystem and memory interface

Table 45.  Interface: hps_emifInterface type: Conduit
Port Name Direction Description
hps_to_emif Input Signals coming from Hard Processor Subsystem to the memory interface
emif_to_hps Output Signals going to Hard Processor Subsystem from the memory interface
hps_to_emif_gp Input Signals coming from Hard Processor Subsystem GPIO to the memory interface
emif_to_hps_gp Output Signals going to Hard Processor Subsystem GPIO from the memory interface