External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.25. clks_sharing_slave_in for DDR3

Core clocks sharing slave input interface

Table 36.  Interface: clks_sharing_slave_inInterface type: Conduit
Port Name Direction Description
clks_sharing_slave_in Input This port should be connected to the core clocks sharing master.