External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.23. cal_debug_out_clk for DDR3

User calibration debug clock interface

Table 34.  Interface: cal_debug_out_clkInterface type: Clock Output
Port Name Direction Description
cal_debug_out_clk Output User clock domain