External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.29. ctrl_user_priority for DDR3

Controller user-requested priority interface

Table 40.  Interface: ctrl_user_priorityInterface type: Conduit
Port Name Direction Description
ctrl_user_priority_hi Input When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests.