External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

8.3.1.6.3. QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals

QDR II, QDR II+ and QDR II+ Xtreme SRAM devices use one address bus (A) for both read and write accesses.