Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

8.3.2.1. Available Address Maps

The following figure shows the default system interconnect address maps for all masters. The figure is not to scale.

Figure 21. Address Maps for System Interconnect Masters

Notes on Address Maps

(1) Transactions on these addresses are directly decoded by the SCU and L2 cache.

(2) This region can be configured to access slaves on the lightweight HPS-to-FPGA bridge, by using the remap register.

(3) This region can be configured to access slaves on the HPS-to-FPGA bridge, by using the remap register.

(4) The MPU accesses SDRAM through a dedicated port.

(5) This region can be configured to access on-chip RAM, by using the remap register.

(6) The following peripherals can master the interconnect:

  • Ethernet MACs
  • USB-2 OTG controllers
  • NAND controllers
  • ETR
  • SD/MMC controller

For the MPU master, either the boot ROM or on-chip RAM maps to address 0x0 and obscures the lowest 64 KB of SDRAM.

At boot time, the MPU does not have access to the SDRAM address space from 0x00010000 to 0x00100000. This is because the MPU's SDRAM access is controlled by the MPU L2 filter registers, which only have a granularity of 1 MB. After booting completes, the MPU can change address filtering to use the lowest 1 MB of SDRAM.

For non-MPU masters, either the on-chip RAM or the SDRAM maps to address 0x0. When mapped to address 0x0, the on-chip RAM obscures the lowest 64 KB of SDRAM for non-MPU masters.