Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

13.1.2. On-Chip RAM Block Diagram and System Integration

Transfers between memory and the NIC-301 L3 interconnect happen through a 64‑bit interface, gated by the l3_main_clk interconnect clock. ECC logic detects single-bit, corrected and double-bit, uncorrected errors. For memory, read acceptance is two, write acceptance is two, and total acceptance is two with a round-robin arbitration.

The entire RAM is either secure or non-secure. Security is enforced by the NIC-301 L3 interconnect.

Figure 42. On-Chip RAM Block Diagram
Note: You must initialize the on-chip RAM before you enable the ECC support to prevent false ECC interrupts triggered by uninitialized bits.