Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

17.3.1. Peripheral Request Interface

The following figure shows that the peripheral request interface consists of a peripheral request bus and a DMAC acknowledge bus that use the prefixes:

  • dr—The peripheral request bus
  • da—The DMAC acknowledge bus
Figure 69. Request and Acknowledge Buses on the Peripheral Request Interface

Both buses use the valid and ready handshake that the AXI protocol describes.

The peripheral uses drtype[1:0] to either:

  • Request a single transfer
  • Request a burst transfer
  • Acknowledge a flush request

The peripheral uses drlast to notify the DMAC that the request on drtype[1:0] is the last request of the DMA transfer sequence. drlast is transferred at the same time as drtype[1:0].

The DMAC can indicate the following using datype[1:0]:

  • When it completes the requested single transfer
  • When it completes the requested burst transfer
  • When it issues a flush request
Note: If you configure the DMAC to provide more than one peripheral request interface, each interface is assigned a unique identifier, _<x> where <x> represents the number of the interface.
For the Synopsys* protocol, the following signals are used in the handshaking protocol:
  • dma_tx_req_n
  • dma_rx_req_n
  • dma_tx_ack_n
  • dma_rx_ack_n
  • dma_tx_single_n
  • dma_rx_single_n