Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

28.3.5. Peripheral Signals Routed to FPGA

You can route the peripheral signals to the FPGA fabric and assign them to the FPGA I/O pins.

The following steps show you how to enable the peripheral signals:

  1. Select FPGA in the peripheral pin multiplexing selection drop-down box.
  2. Export the peripheral signals out of Platform Designer (Standard) system.
  3. In the Intel® Quartus® Prime software, connect the signals to the FPGA I/O pins.
Note: When routed to the FPGA, some HPS peripherals require additional pipeline support in the connected soft logic. Routing into the FPGA circumvents the pipelining available in the HPS I/O. Refer to the relevant HPS peripheral chapter for details.