Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

10.9.1. Cortex-A9 MPU Subsystem Address Map

The Cortex* -A9 MPU subsystem registers reside within the address range from 0xFFFEC000 to 0xFFFEEFFF.

Table 72.  MPU Module Address Range
Module Instance Start Address End Address

MPU

0xFFFEC000 0xFFFEEFFF
Table 73.  Cortex-A9 MPU Submodule Register Space
Submodule Instance Description Start Address End Address

SCU

This address space is allocated for the Snoop Control Unit registers. 0xFFFEC000 0xFFFEC0FF

GIC

This address space is allocated for the Generic Interrupt Controller (GIC) registers. 0xFFFEC100 0xFFFEC1FF

Global Timer

This address space is allocated for the Global Timer registers. 0xFFFC200 0xFFFEC2FF

Reserved

This address space is reserved. 0xFFFEC300 0xFFFEC5FF

Private Timers and Watchdog Timers

This is the address space is allocated for private timer and watchdog timer registers. 0xFFFEC600 0xFFFEC6FF

Reserved

This address space is reserved.
Note: Any access to this region causes a SLVERR abort exception.
0xFFFEC700 0xFFFEC7FF

Interrupt Distributor

This address space is allocated for the interrupt distributor registers. 0xFFFED000 0xFFFEDFFF

Reserved

This address space is reserved. 0xFFFEE000 0xFFFEEFFF