Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

10.4.2.6. Control of the AXI User Sideband Signals

The ACP ID mapper module allows control of the AXI user sideband signal values. Not all masters drive these signals, so the ACP ID mapper makes it possible to drive the 5‑bit user sideband signal with either a default value (in dynamic mode) or specific values (in fixed mode). The sideband signals are controlled through the ACP port. Sideband signals AWUSER[4:1] convey the inner cache attributes and AWUSER[0] determines whether the transaction is a shared cache access.

There are registers available to configure the default values of the user sideband signals for all transactions, and fixed values of these signals for particular transactions in fixed mapping mode. In dynamic mode, the user sideband signals of incoming transactions are mapped with the default values stored in the register. In fixed mapping mode, the input ID of the transaction is mapped to the 3‑bit output ID and the user sideband signals of the transaction are mapped with the values stored in the register that corresponds to the output ID. One important exception, however, is that the ACP ID mapper always allows user sideband signals from the FPGA‑to‑HPS bridge to pass through to the ACP regardless of the user sideband value associated with the ID.
Note: For coherent, cacheable reads or writes, the user field of the vid*rd and vid*wr registers must be set to a binary value of 5'b11111 (coherent write back, write allocate inner cache attribute). This configuration ensures that the inner cache policy matches the policy used for cacheable data written by the processor.