Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

29.1.3. FPGA-to-HPS SDRAM Interface

The FPGA-to-HPS SDRAM interface is a direct connection between the FPGA fabric and the HPS SDRAM controller. This interface is highly configurable, allowing a mix between number of ports and port width. The interface supports both AXI* -3 and Avalon-MM protocols.

Table 230.  FPGA-to-HPS SDRAM Interfaces and Clocks

Interface Name

Description

Associated Clock Interface

f2h_sdram0_data

SDRAM AXI* or Avalon-MM port 0

f2h_sdram0_clock

f2h_sdram1_data

SDRAM AXI* or Avalon-MM port 1

f2h_sdram1_clock

f2h_sdram2_data

SDRAM AXI* or Avalon-MM port 2

f2h_sdram2_clock

f2h_sdram3_data

SDRAM AXI* or Avalon-MM port 3

f2h_sdram3_clock

f2h_sdram4_data

SDRAM AXI* or Avalon-MM port 4

f2h_sdram4_clock

f2h_sdram5_data

SDRAM AXI* or Avalon-MM port 5

f2h_sdram5_clock

The FPGA-to-HPS SDRAM interface is a configurable interface to the multi-port SDRAM controller.

The total data width of all interfaces is limited to a maximum of 256 bits in the read direction and 256 bits in the write direction. The interface is implemented as four 64-bit read ports and four 64-bit write ports. As a result, the minimum data width used by the interface is 64 bits, regardless of the number or type of interfaces.

You can configure this interface the following ways:

  • AXI* -3 or Avalon-MM protocol
  • Number of interfaces
  • Data width of interfaces

The FPGA-to-HPS SDRAM interface supports six command ports, allowing up to six Avalon-MM interfaces or three bidirectional AXI* interfaces.

Each command port is available either to implement a read or write command port for AXI* , or to form part of an Avalon-MM interface.

You can use a mix of Avalon-MM and AXI* interfaces, limited by the number of command/data ports available. Some AXI* features are not present in Avalon-MM interfaces.

This interface has an address width of 32 bits. To access existing Avalon-MM/ AXI* masters, you can use the Address Span Extender.

Note: If you connect the HPS-to-SDRAM interface with the Avalon MM pipeline bridge, you must set the bridge Addressing Unit setting to Word.