Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

19.5.4.2.2. OUT Transactions

For an OUT transaction, the application performs the following steps:

  1. Enables the endpoint
  2. Waits for the packet received interrupt from the USB OTG controller
  3. Retrieves the packet from the receive FIFO buffer

When an OUT token or PING token is received on an endpoint where the receive FIFO buffer does not have sufficient space, the controller performs the following steps:

  1. Generates an interrupt
  2. Returns a NAK handshake to USB host

If sufficient space is available, the controller stores the data in the receive FIFO buffer and returns an ACK handshake to the USB link.

According to the USB 2.0 specifications, to transmit two packets back-to-back, the inter-packet delay must be a minimum of 88 bit times, measured at the first receptacle of the host. This guarantees an inter-packet delay of at least 32 bit times at all devices (when receiving these back-to-back packets). For the device controller to support the worst-case inter-packet delay of 32 bit times and isochronous OUT endpoints across multiple layers of hubs, the controller must operate in 8-bit UTMI mode and the AHB frequency must be at least 96 MHz.

Alternatively, choose the AHB clock frequency based on your targeted use case and supported number of hubs. However, in both cases the 8-bit PHY data interface should be used for operation using the SoC.
Table 195.  Supported Number of Hubs Tiers for Different PHY and AHB Clock Frequencies
Number of Hub Levels Worst Case IPG Possible at Hub/Host Downstream Port (in bit times) Minimum HCLK Frequency Required (in MHz)
UTMI Data Width = 8 UTMI Data Width = 16
No Hub 88 30 110
1 78.4 32 213
2 68.8 37 -
3 59.2 44 -
4 49.6 54 -
5 40 70 -