Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

8.3.8. Interconnect Slave Properties

The interconnect connects to various slave interfaces through the L3 interconnect, L3 slave peripheral switch, and the five L4 peripheral buses. After reset, all slave interfaces are set to the secure state.

The interconnect provides FIFO buffers with clock crossing adapters. Refer to "FIFO Buffers and Clock Crossing" for details.

Table 38.  Interconnect Slave Interfaces

Slave

I/F Width

Clock

Mastered By

Acceptance 17

Buffer Depth

18

Type

SDRAM subsystem CSR

32

l4_sp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

SP timer 0/1

32

l4_sp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

I2C 0/1/2/3

32

l4_sp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

UART 0/1

32

l4_sp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

CAN 0/1

32

l4_sp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

GPIO 0/1/2

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

ACP ID mapper CSR

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

FPGA manager CSR

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

DAP CSR

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

Quad SPI flash CSR

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

SD/MMC CSR

32

l4_mp_clk

L4 SP bus master

1, 1, 1

2, 2, 2

APB

EMAC 0/1 CSR

32

l4_mp_clk

L4 MP bus master

1, 1, 1

2, 2, 2

APB

System manager

32

osc1_clk

L4 OSC1 bus master

1, 1, 1

2, 2, 2

APB

OSC1 timer 0/1

32

osc1_clk

L4 OSC1 bus master

1, 1, 1

2, 2, 2

APB

Watchdog 0/1

32

osc1_clk

L4 OSC1 bus master

1, 1, 1

2, 2, 2

APB

Clock manager

32

osc1_clk

L4 OSC1 bus master

1, 1, 1

2, 2, 2

APB

Reset manager

32

osc1_clk

L4 OSC1 bus master

1, 1, 1

2, 2, 2

APB

DMA secure CSR

32

l4_main_clk

L4 main bus master

1, 1, 1

2, 2, 2

APB

DMA nonsecure CSR

32

l4_main_clk

L4 main bus master

1, 1, 1

2, 2, 2

APB

SPI slave 0/1

32

l4_main_clk

L4 main bus master

1, 1, 1

2, 2, 2

APB

Scan manager

32

spi_m_clk

L4 main bus master

1, 1, 1

2, 2, 2

APB

SPI master 0/1

32

spi_m_clk

L4 main bus master

1, 1, 1

2, 2, 2

APB

Lightweight HPS-to-FPGA bridge

32

l4_main_clk

L3 slave peripheral switch

16, 16, 32

2, 2, 2, 2, 2

AXI

USB OTG 0/1

32

usb_mp_clk

L3 slave peripheral switch

1, 1, 1

2, 2, 2

AHB

NAND CSR

32

nand_x_clk

L3 slave peripheral switch

1, 1, 1

2, 2, 2

AXI

NAND command and data

32

nand_x_clk

L3 slave peripheral switch

1, 1, 1

2, 2, 2

AXI

Quad SPI flash data

32

l4_mp_clk

L3 slave peripheral switch

1, 1, 1

2, 2, 2

AHB

FPGA manager data

32

cfg_clk

L3 interconnect

1, 2, 3

2, 2, 2, 32, 2

AXI

HPS-to-FPGA bridge

64

l3_main_clk

L3 interconnect

16, 16, 32

2, 2, 6, 6, 2

AXI

ACP ID mapper data

64

mpu_l2_ram_clk

L3 interconnect

13, 5, 18

2, 2, 2, 2, 2

AXI

STM

32

dbg_at_clk

L3 interconnect

1, 2, 2

2, 2, 2, 2, 2

AXI

On-chip boot ROM

32

l3_main_clk

L3 interconnect

1, 1, 2

0, 0, 0, 0, 0

AXI

On-chip RAM

64

l3_main_clk

L3 interconnect

2, 2, 2

0, 0, 0, 8, 0

AXI

SDRAM subsystem L3 data

32

l3_main_clk

L3 interconnect

16, 16, 16

2, 2, 2, 2, 2

AXI

17 Acceptance is based on the number of read, write, and total transactions.
18 The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth is based on W, A, and D channels.