Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

29.5.1. DMA Controller Interface

The DMA controller interface allows soft IP in the FPGA fabric to communicate with the DMA controller in the HPS. You can configure up to eight separate interface channels.

  • f2h_dma_req0—FPGA DMA controller peripheral request interface 0
  • f2h_dma_req1—FPGA DMA controller peripheral request interface 1
  • f2h_dma_req2—FPGA DMA controller peripheral request interface 2
  • f2h_dma_req3—FPGA DMA controller peripheral request interface 3
  • f2h_dma_req4—FPGA DMA controller peripheral request interface 4
  • f2h_dma_req5—FPGA DMA controller peripheral request interface 5
  • f2h_dma_req6—FPGA DMA controller peripheral request interface 6
  • f2h_dma_req7—FPGA DMA controller peripheral request interface 7

Each of the DMA peripheral request interface contains the following three signals:

  • f2h_dma_req—This signal is used to request burst transfer using the DMA
  • f2h_dma_single—This signal is used to request single word transfer using the DMA
  • f2h_dma_ack—This signal indicates the DMA acknowledgment upon requests from the FPGA